PDF NLSV8T240 Data sheet ( Hoja de datos )

Número de pieza	NLSV8T240
Descripción	8-Bit Dual-Supply Non-Inverting Level Translator
Fabricantes	ON Semiconductor
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No Preview Available ! NLSV8T240 8-Bit Dual-Supply Inverting Level Translator The NLSV8T240 is a 8−bit configurable dual−supply voltage level translator. The input An and output Bn ports are designed to track two different power supply rails, VCCA and VCCB respectively. Both supply rails are configurable from 0.9 V to 4.5 V allowing universal low−voltage translation from the input An to the output Bn port. Features • Wide VCCA and VCCB Operating Range: 0.9 V to 4.5 V • High−Speed w/ Balanced Propagation Delay • Inputs and Outputs have OVT Protection to 4.5 V • Non−preferential VCCA and VCCB Sequencing • Outputs at 3−State until Active VCC is Reached • Power−Off Protection • Outputs Switch to 3−State with VCCB at GND • Ultra−Small Packaging: 4.0 mm x 2.0 mm UDFN20 • This is a Pb−Free Device Typical Applications • Mobile Phones, PDAs, Other Portable Devices Important Information • ESD Protection for All Pins: HBM (Human Body Model) > 7000 V VCCA VCCB A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 www.DataASh7 eet4U.com A8 OE Figure 1. Logic Diagram B7 B8 http://onsemi.com MARKING DIAGRAM UDFN20 MU SUFFIX CASE 517AK LBMG G LB = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT VCCA 1 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 GND 10 20 VCCB 19 B1 18 B2 17 B3 16 B4 15 B5 14 B6 13 B7 12 B8 11 OE (Top View) ORDERING INFORMATION Device Package Shipping† NLSV8T240MUTAG UDFN20 3000/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2008 July, 2008 − Rev. 0 1 Publication Order Number: NLSV8T240/D 1 page Pulse Generator NLSV8T240 VCC DUT RL CL RL VCCO x 2 OPEN GND Figure 2. AC (Propagation Delay) Test Circuit Test Switch tPLH, tPHL OPEN tPLZ, tPZL VCCO x 2 tPHZ, tPZH GND CL = 15 pF or equivalent (includes probe and jig capacitance) RL = 2 kW or equivalent ZOUT of pulse generator = 50 W Input (An) Output (Bn) Vm tPLH Vm Vm tPHL Vm Waveform 1 − Propagation Delays tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns VIH 0V VOH VOL OEn Output (Bn) tPZH Vm Vm tPHZ Vm Output (Bn) tPZL tPLZ Vm VIH 0V VVOY H ≈0V ≈ VCC VVOX L Waveform 2 − Output Enable and Disable Times tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns Figure 3. AC (Propagation Delay) Test Circuit Waveforms www.DataSheSety4mUb.cool m VmA VmB VX VY 3.0 V – 4.5 V VCCA/2 VCCB/2 VOL x 0.1 VOH x 0.9 2.3 V − 2.7 V VCCA/2 VCCB/2 VOL x 0.1 VOH x 0.9 VCC 1.65 V − 1.95 V VCCA/2 VCCB/2 VOL x 0.1 VOH x 0.9 1.4 V − 1.6 V VCCA/2 VCCB/2 VOL x 0.1 VOH x 0.9 0.9 V − 1.3 V VCCA/2 VCCB/2 VOL x 0.1 VOH x 0.9 http://onsemi.com 5 5 Page

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