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CAT34AC02 PDF даташит

Спецификация CAT34AC02 изготовлена ​​​​«Catalyst Semiconductor» и имеет функцию, называемую «2K-Bit SMBus EEPROM».

Детали детали

Номер произв CAT34AC02
Описание 2K-Bit SMBus EEPROM
Производители Catalyst Semiconductor
логотип Catalyst Semiconductor логотип 

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CAT34AC02 Даташит, Описание, Даташиты
Preliminary Information
CAT34AC02
2K-Bit SMBus EEPROM for ACR Card Configuration
FEATURES
ALOGEN FR
LEA
D
F
R
E
E
TM
s 400 kHz (5V) and 100 kHz (1.8V) SMBus
compatible
s 1.8 to 6.0 volt operation
s Low power CMOS technology
– zero standby current
s 16-byte page write buffer
s Industrial, automotive and extended
temperature ranges
s Self-timed write cycle with auto-clear
s 1,000,000 program/erase cycles
s 100 year data retention
s 8-pin DIP, 8-pin SOIC and 8-pin TSSOP packages
s 256 x 8 memory organization
s Hardware write protect
DESCRIPTION
The CAT34AC02 is a 2K-bit Serial CMOS EEPROM
internally organized as 256 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces de-
vice power requirements. The CAT34AC02 features a
16-byte page write buffer. The device operates via the
SMBus serial interface for ACR card configuration and
is available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP
packages.
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, W)
BLOCK DIAGRAM
EXTERNAL LOAD
A0
A1
A2
VSS
1
2
3
4
8 VCC
A0
7 WP
A1
6 SCL
A2
5 SDA
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
TSSOP Package (U, Y)
MSOP Package (R, Z)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
18
27
36
45
SDA
WP
START/STOP
LOGIC
CONTROL
LOGIC
XDEC
E2PROM
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2 Device Address Inputs
SDA
Serial Data/Address
www.DaStaCShLeet4U.com Serial Clock
WP Write Protect
VCC +1.8V to +6.0V Power Supply
VSS Ground
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc No. 1025, Rev. E









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CAT34AC02 Даташит, Описание, Даташиты
CAT34AC02
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
55°C to +125°C
Storage Temperature ....................... 65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... 2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... 2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
*COMMENT
Stresses above those listed under Absolute Maximum
Ratingsmay cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
RELIABILITY CHARACTERISTICS
Symbol Parameter
Reference Test Method
Min
NEND(3)
TDR(3)
VZAP(3)
ILTH(3)(4)
Endurance
MIL-STD-883, Test Method 1033 1,000,000
Data Retention
MIL-STD-883, Test Method 1008 100
ESD Susceptibility MIL-STD-883, Test Method 3015 2000
Latch-up
JEDEC Standard 17
100
Typ
Max Units
Cycles/Byte
Years
Volts
mA
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Symbol Parameter
Test Conditions
Min
Typ
Max Units
ICC Power Supply Current (Read)
fSCL = 100 kHz
1 mA
ICC
ISB(5)
Power Supply Current (Write)
Standby Current (VCC = 5.0V)
fSCL = 100 kHz
VIN = GND or VCC
3 mA
0 µA
ILI Input Leakage Current
VIN = GND to VCC
10 µA
ILO Output Leakage Current
VOUT = GND to VCC
10 µA
VIL Input Low Voltage
1
VCC x 0.3
V
VIH Input High Voltage
VCC x 0.7
VCC + 0.5 V
VOL1 Output Low Voltage (VCC = 3.0V)
IOL = 3 mA
0.4 V
VOL2 Output Low Voltage (VCC = 1.8V)
IOL = 1.5 mA
0.5 V
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Parameter
Test Conditions Min Typ Max Units
CI/O(3) Input/Output Capacitance (SDA)
VI/O = 0V
8 pF
www.DaCtaINSh(3e)et4UI.ncopmut Capacitance (A0, A1, A2, SCL)
VIN = 0V
6 pF
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to VCC +1V.
(5) Standby Current (ISB) = 0µA (<900nA).
Doc. No. 1025, Rev. E
2









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CAT34AC02 Даташит, Описание, Даташиты
CAT34AC02
A.C. CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Read & Write Cycle Limits
Symbol Parameter
1.8V-6.0V, 2.5V - 6.0V
Min Max
FSCL
T (1)
I
tAA
t (1)
BUF
Clock Frequency
Noise Suppression Time Constant at
SCL, SDA Inputs
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before a
New Transmission Can Start
4.7
100
100
3.5
t
HD:STA
tLOW
tHIGH
tSU:STA
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a
Repeated Start Condition)
4
4.7
4
4.7
tHD:DAT
tSU:DAT
t (1)
R
t (1)
F
tSU:STO
tDH
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0
50
1
300
4
100
Power-Up Timing(1)(2)
Symbol Parameter
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
Min
4.5V - 5.5V
Min Max
400
100
1
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
0.6
100
Typ Max
1
1
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Units
ms
ms
Write Cycle Limits
Symbol Parameter
tWR Write Cycle Time
www.DataSheet4U.com
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Min Typ Max Units
4 5 ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
3 Doc No. 1025, Rev. E










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