SC3042B Datasheet PDF - RF Monolithics
| Part Number | SC3042B | |
| Description | 624.0 MHz Differential Sine-Wave Clock | |
| Manufacturers | RF Monolithics | |
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Preliminary
• Quartz SAW Frequency Stability
• Fundamental Fixed Frequency
• Very Low Jitter and Power Consumption
• Rugged, Miniature, Surface-Mount Case
• Low-Voltage Power Supply (3.3 VDC)
This digital clock is designed for use in high-speed communications timing systems. Fundamental-mode
oscillation is made possible by surface-acoustic-wave (SAW) technology. The design results in low jitter,
compact size, and low power consumption. Differential outputs provide a sine wave that is capable of driving
50 Ω loads.
Absolute Maximum Ratings
Rating
Value
Units
Power Supply Voltage (VCC at Terminal 1)
Input Voltage (ENABLE at Terminal 8)
0 to +4.0
0 to +4.0
VDC
VDC
Case Temperature (Powered or Storage)
-40 to +85
°C
SC3042B
624.0 MHz
Differential
Sine-Wave
Clock
SMC-8 Case
Electrical Characteristics
Characteristic
Output Frequency
Q and Q Output
Q and Q Period Jitter
Output (Disabled)
Absolute Frequency
Tolerance from 624.0 MHz
Voltage into 50Ω (VSWR ≤ 1.2)
Operating Load VSWR
Symmetry
Harmonic Spurious
Nonharmonic Spurious
No Noise on VCC
200 mVP-P from 1 MHz to ½ fO on
Amplitude into 50 Ω
Output DC Resistance (between Q & Q)
ENABLE (Terminal 14)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Propagation Delay
DC Power Supply
Operating Voltage
Operating Current
Operating Ambient Temperature
Lid Symbolization (YY = Year, WW = Week)
Sym
fO
ΔfO
VO
VIH
VIL
IIH
IIL
tPD
VCC
ICC
TA
Notes
1, 2
Minimum
623.875
Typical
Maximum
624.125
±200
0.60
1, 3
1.1
2:1
3, 4, 5
49
51
3, 4, 6
-30
-60
3, 4, 6, 7
15 30
3, 4, 7, 8
35
3, 9 75
3 50
VCC-0.1
VCC
VCC+0.1
0.0 0.20
3, 9 3 5
-1
1
+3.13
+3.30
+3.47
1, 3
20 40
1, 3 0
+70
RFM SC3042B 624.00 MHz YYWW
Units
MHz
ppm
VP-P
%
dBc
dBc
psP-P
psP-P
mVP-P
KΩ
V
V
mA
mA
ms
VDC
mA
°C
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
NOTES:
1. Unless otherwise noted, all specifications include any combination of load 6. Jitter and other spurious outputs induced by externally generated electrical
VSWR, VCC, and TA. In addition, Q and Q are terminated into 50 Ω loads
noise on VCC or mechanical vibration are not included. Dedicated external
www.DtoagtraoSuhnde.et(4SUee.:coTmypical Test Circuit.)
voltage regulation and careful PCB layout are recommended for optimum
2. One or more of the following United States patents apply: 4,616,197;
performance.
4,670,681; 4,760,352.
7. Applies to period jitter of Q and Q. Measurements are made with the
3. The design, manufacturing process, and specifications of this device are
Tektronix CSA803 signal analyzer with at least 1000 samples.
subject to change without notice.
4. Only under the nominal conditions of 50 Ω load impedance with VSWR ≤
1.2 and nominal power supply voltage.
5. Symmetry is defined as the pulse width (in percent of total period)
measured at the 50% points of Q or Q. (See: Timing Definitions.)
8. Period jitter measured with a 200 mVP-P sine wave swept from 1 MHz to
one-half of fO at the VCC power supply terminal.
9. The outputs are enabled when Terminal 8 is at logic HIGH. Propagation
delay is defined as the time from the 50% point on the rising edge of
ENABLE to the 90% point on the rising edge of the output amplitude or as
the fall time from the 50% point to the 10% point. (SEE: Timing
Definitions.)
www.RFM.com E-mail: [email protected]
©2008 by RF Monolithics, Inc.
Page 1 of 2
SC3042B - 3/27/08
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for SC3042B electronic component. |
| Information | Total 2 Pages | |
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| Download | [ SC3042B.PDF Datasheet ] | |
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