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N5434A PDF даташит

Спецификация N5434A изготовлена ​​​​«Agilent(Hewlett-Packard)» и имеет функцию, называемую «FPGA Dynamic Probe».

Детали детали

Номер произв N5434A
Описание FPGA Dynamic Probe
Производители Agilent(Hewlett-Packard)
логотип Agilent(Hewlett-Packard) логотип 

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N5434A Даташит, Описание, Даташиты
Agilent Technologies InfiniiVision MSO
N5434A FPGA Dynamic Probe for Altera
Data Sheet
Figure 1. FPGA dynamic probe for Altera used in conjunction with an InfiniiVision
6000 or 7000 Series MSO provides an effective solution for simple through complex
debugging of systems incorporating Altera FPGAs.
The challenge
You rely on the insight a MSO
(mixed-signal oscilloscope)
provides to understand the
behavior of your FPGA in
the context of the surrounding
system. Design engineers
typically take advantage of the
programmability of the FPGA to
route internal nodes to a small
number of physical pins for
www.DadteabShuegegti4nUg..cWomhile this approach
is very useful, it has significant
limitations.
• Since pins on the FPGA
are typically an expensive
resource, there are a relatively
small number available for
debug. This limits internal
visibility (i.e. one pin is
required for each internal
signal to be probed).
• When you need to access
different internal signals,
you must change your design
to route these signals to the
available pins. This can be time
consuming and can affect the
timing of your FPGA design.
• Finally, the process required
to map the signal names from
your FPGA design to the
MSO digital channel labels is
manual and tedious.
When new signals are routed
out, you need to manually
update these signal names
on the MSO, which takes
additional time and is a
potential source of confusing
errors.









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N5434A Даташит, Описание, Даташиты
Debug your FPGAs faster and more effectively with a MSO
FPGA dynamic probe lets you:
View internal activity – With the
digital channels on your MSO, you
are normally limited to measuring
signals at the periphery of the
FPGA. With the FPGA dynamic
probe, you can now access signals
internal to the FPGA. You can
measure up to 256 internal
signals for each external pin
dedicated to debug, unlocking
visibility into your design that
you never had before.
Make multiple measurements in
seconds – Moving probe points
internal to an FPGA used to be
time consuming. Now, in less than
a second, you can easily measure
different sets of internal signals
without design changes. FPGA
timing stays constant when you
select new sets of internal signals
for probing.
Probe outputs
on FPGA pins
PC board
FPGA
LAI
Insert LAI core with
Altera Quartus II
JTAG
SW application can be
licensed to a particular
PC or particular MSO
SW application installed
on a PC connected to
6000 or 7000 Series MSO
USB
LAN
GPIB
Parallel
or USB
Figure 2. The FPGA dynamic probe requires Altera’s Quartus II design software with its
LAI (logic analyzer interface) and Altera programming hardware setup. The Quartus II
(ver. 6.0 or higher) LAI allows you to create and insert a debug core that interacts with
the FPGA dynamic probe application on your MSO. The FPGA dynamic probe controls
which group of internal signals to measure via the Altera programming hardware
connected to the JTAG port of the FPGA.
Leverage the work you did in your
design environment – The FPGA
dynamic probe maps internal
signal names from your FPGA
design tool to your Agilent MSO.
Eliminate unintentional mistakes
and save hours of time with this
automatic setup of signal and bus
names on your MSO.
1-256
1-256
1-256
1-256
1-256 To FPGA pins
www.DataSheet4U.com
JTAG
Change signal bank
selection via JTAG
Figure 3. Access up to 256 internal signals for each debug pin. Signal
banks all have identical width (1 to 256 signals wide) determined by
the number of device pins you devote for debug. Each pin provides
sequential access to one signal from every input bank. MSO6000
series can acquire up to 16 signals using digital channels.
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N5434A Даташит, Описание, Даташиты
A quick tour of the application
Design step 1: Configure the logic
analyzer interface file and core
parameters
You need to create a Altera LAI
file with MSO in Quartus II. This
file defines the interface that
builds a connection between
the internal FPGA signals and
the MSO digital channels. You
can then configure the core
parameters, which include
number of pins, number of signal
banks, the type of measurement
(state or timing), clock and the
power-up state.
Design step 2: Map the Altera LAI
core outputs to available I/O pins
Use Pin Planner in Quartus II to
assign physical pin locations for
the LAI.
www.DataSheet4U.com
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Номер в каталогеОписаниеПроизводители
N5434AFPGA Dynamic ProbeAgilent(Hewlett-Packard)
Agilent(Hewlett-Packard)

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