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PDF HMMC-3024 Data sheet ( Hoja de datos )
| Número de pieza | HMMC-3024 | |
| Descripción | DC-12 GHz High Efficiency GaAs HBT MMIC Divide-by-4 Prescaler | |
| Fabricantes | Agilent(Hewlett-Packard) | |
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Agilent HMMC–3024
DC–12 GHz High Efficiency
GaAs HBT MMIC
Divide–by–4 Prescaler
1GC1-8007
Data Sheet
Features
• Wide Frequency Range:
0.2-12 GHz
• High Input Power Sensitivity:
On-chip pre- and post-amps
-25 to +10 dBm (1–8 GHz)
-15 to +18 dBm (8–10 GHz)
-10 to +2 dBm (10–12 GHz)
• Dual-mode Pout: (Chip Form)
0 dBm (0.5 Vp–p) @ 40 mA
-6.0 dBm (0.25 Vp–p) @ 30 mA
• Low Phase Noise:
-153 dBc/Hz @ 100 kHz Offset
• (+) or (-) Single Supply Bias
Operation
• Wide Bias Supply Range:
4.5 to 6.5 volt operating range
• Differential I/0 with on-chip
50 Ω matching
Description
The HMMC-3024 GaAs HBT MMIC
prescaler offers dc to 12 GHz fre-
quency translation for use in
communications and EW systems
incorporating high-frequency PLL
oscillator circuits and signal-path
down conversion applications.
The prescaler provides a large input
power sensitivity window and low
phase noise. In addition to the fea-
www.DatatuSrheeselti4sUte.dcoambove the device offers
an input disable contact pad to elimi-
nate any self-oscillation condition.
Chip Size:
1330 x 440 µm (52.4 x 17.3 mils)
Chip Size Tolerance: ± 10 µm (± 0.4 mils)
Chip Thickness: 127 ± 15 µm (5.0 ± 0.6 mils)
Pad Dimensions: 70 x 70 µm (2.8 x 2.8 mils)
Absolute Maximum Ratings1
(@ TA = 25°C, unless otherwise indicated)
Symbol
Parameters/Conditions
Min.
Max.
Units
VCC Bias supply voltage
+7 volts
VEE
Bias supply voltage
-7
volts
VCC - VEE
Bias supply delta
0 +7 volts
VDisable
Pre-amp disable voltage
VEE VCC volts
VLogic
Logic threshold voltage
VCC -1.5 VCC -1.2 volts
Pin(CW)
CW RF input power
+10 dBm
VRFin
TBS2
DC input voltage
(@ RFin or RFin ports)
Backside operating temperature
-40
VCC ±0.5 volts
+85 °C
Tst
Storage temperature
-65 +165 °C
Tmax
Maximum assembly temperature
310 °C
Notes
(60 s max.)
1. Operation in excess of any parameter limit (except TBS) may cause permanent damage to the device.
2. MTTF > 1 x 106 hours @ TBS ≤ 85°C. Operation in excess of maximum operating temperature (TBS) will degrade MTTF.
1 page  
2. VLogic ECL Contact Pad
Under normal conditions
no connection or external bias
is required to this pad and it
is self-biased to the on-chip ECL
logic threshold voltage
(VCC -1.35 V). The user can
provide an external bias to this pad
(1.5 to 1.2 volts less than VCC) to force
the prescaler to
operate at a system generated logic
threshold voltage.
3. Input Disable Feature
If an RF signal with sufficient signal-
to-noise ratio is present at the RF
input, the prescaler will operate and
provide a divided output equal to the
input frequency divided by the divide
modulus. Under certain “ideal” condi-
tions where the input is well matched
at the right input frequency, the
device may “self-oscillate,” especially
under small signal input powers or
with only noise present at the input.
This “self-oscillation” will produce a
undesired output signal also known
as a false trigger. By applying an
external bias to the input disable
contact pad (more positive than VCC -
1.35 V), the input preamplifier stage is
locked into either logic “high” or logic
“low” preventing frequency division
and any self-oscillation frequency
which may be present.
4. Input dc Offset
Another method used to prevent false
triggers or self-oscillation
conditions is to apply a 20 to
100 mV dc offset voltage between
the RFin and RFin ports. This prevents
noise or spurious low level signals
from triggering the divider.
www.DatAaSdhdienegt4aU1.c0oKmΩ resistor between the
unused RF input to a contact point at
the VEE potential will result in an off-
set of ≈25 mV between the RF inputs.
Note however, that the input sensitivity
will be reduced slightly due to the
presence of this offset.
Assembly Techniques
Figure 3 shows the chip assembly
diagram for single-ended I/O opera-
tion through 12 GHz for either positive
or negative bias supply operation. In
either case the supply contact to the
chip must be capacitively bypassed to
provide good input sensitivity and low
input power feedthrough. Independent
of the bias applied to the device, the
backside of the chip should always be
connected to both a good RF ground
plane and a good thermal heat sinking
region on the mounting surface.
All RF ports are dc connected
on-chip to the VCC contact through
on-chip 50 Ω resistors. Under any
bias conditions where VCC is not dc
grounded, the RF ports should be ac
coupled via series capacitors mounted
on the thin-film substrate at each RF
port. Only under bias conditions where
VCC is dc grounded (as is typical for
negative bias supply operation) may
the RF ports be direct coupled to adja-
cent circuitry or in some cases, such
as level shifting to subsequent stages.
In the latter case the device backside
may be “floated” and bias applied as
the difference between VCC and VEE.
All bonds between the device and this
bypass capacitor should be as short
as possible to limit the inductance.
For operation at frequencies below 1
GHz, a large value capacitor must be
added to provide proper RF bypassing.
Due to on-chip 50 Ω matching resis-
tors at all four RF ports, no external
termination is required on any unused
RF port. However, improved “Spit-
back” performance (~20 dB) and
input sensitivity can be achieved by
terminating the unused RFout port to
VCC through 50 Ω (positive supply) or
to ground via
a 50 Ω termination (negative
supply operation).
GaAs MMICs are ESD sensitive.
ESD preventive measures must be
employed in all aspects of storage,
handling, and assembly.
MMIC ESD precautions, handling
considerations, die attach and bond-
ing methods are critical factors in suc-
cessful GaAs MMIC performance and
reliability.
Agilent application note #54, “GaAs
MMIC ESD, Die Attach and Bonding
Guidelines” provides basic
information on these subjects.
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HMMC-3024.PDF ] | |
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