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PDF HD64F2505 Data sheet ( Hoja de datos )
| Número de pieza | HD64F2505 | |
| Descripción | 16-Bit Single-Chip Microcomputer | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
www.DataSheet4U.com
1 page  
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in
the manual.
⎯ The input pins of CMOS products are generally in the high-impedance state. In
operation with an unused pin in the open-circuit state, extra electromagnetic noise is
induced in the vicinity of LSI, an associated shoot-through current flows internally, and
malfunctions may occur due to the false recognition of the pin state as an input signal.
Unused pins should be handled as described under Handling of Unused Pins in the
manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
⎯ The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the
states of pins are not guaranteed from the moment when power is supplied until the
reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on
reset function are not guaranteed from the moment when power is supplied until the
power reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
⎯ The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has
become stable. When switching the clock signal during program execution, wait until the
target clock signal has stabilized.
⎯ When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization
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Moreover, when switching to a clock signal produced
(or by an external oscillator) while program execution
with
is in
an
progress,
wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number,
confirm that the change will not lead to problems.
⎯ The characteristics of MPU/MCU in the same group but having different type numbers
may differ because of the differences in internal memory capacity and layout pattern.
When changing to products of different type numbers, implement a system-evaluation
test for each of the products.
Rev. 6.00 Sep. 24, 2009 Page iii of xlvi
REJ09B0099-0600
5 Page 
Contents
Section 1 Overview..................................................................................................1
1.1 Features.................................................................................................................................. 1
1.2 Internal Block Diagram.......................................................................................................... 2
1.3 Pin Arrangements................................................................................................................... 6
1.3.1 Pin Arrangements ..................................................................................................... 6
1.3.2 Pin Arrangements in Each mode............................................................................. 11
1.3.3 Pin Functions .......................................................................................................... 17
Section 2 CPU........................................................................................................25
2.1 Features................................................................................................................................ 25
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................... 26
2.1.2 Differences from H8/300 CPU ............................................................................... 27
2.1.3 Differences from H8/300H CPU............................................................................. 27
2.2 CPU Operating Modes......................................................................................................... 28
2.2.1 Normal Mode.......................................................................................................... 28
2.2.2 Advanced Mode...................................................................................................... 29
2.3 Address Space...................................................................................................................... 32
2.4 Register Configuration......................................................................................................... 33
2.4.1 General Registers.................................................................................................... 34
2.4.2 Program Counter (PC) ............................................................................................ 35
2.4.3 Extended Control Register (EXR) .......................................................................... 35
2.4.4 Condition-Code Register (CCR)............................................................................. 36
2.4.5 Initial Values of CPU Registers .............................................................................. 37
2.5 Data Formats........................................................................................................................ 38
2.5.1 General Register Data Formats ............................................................................... 38
2.5.2 Memory Data Formats ............................................................................................ 40
2.6 Instruction Set ...................................................................................................................... 40
2.6.1 Table of Instructions Classified by Function .......................................................... 42
www2..6D.2ataSBheaesti4cUIn.csotrmuction Formats ....................................................................................... 51
2.7 Addressing Modes and Effective Address Calculation........................................................ 52
2.7.1 Register Direct⎯Rn ............................................................................................... 53
2.7.2 Register Indirect⎯@ERn ....................................................................................... 53
2.7.3 Register Indirect with Displacement⎯@(d:16, ERn) or @(d:32, ERn)................. 53
2.7.4 Register Indirect with Post-Increment or Pre-Decrement⎯@ERn+ or @-ERn..... 53
2.7.5 Absolute Address⎯@aa:8, @aa:16, @aa:24, or @aa:32....................................... 54
2.7.6 Immediate⎯#xx:8, #xx:16, or #xx:32.................................................................... 54
Rev. 6.00 Sep. 24, 2009 Page ix of xlvi
REJ09B0099-0600
11 Page | ||
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| PDF Descargar | [ Datasheet HD64F2505.PDF ] | |
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