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PDF SAF3560 Data sheet ( Hoja de datos )
| Número de pieza | SAF3560 | |
| Descripción | Terrestrial digital radio processor | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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SAF3560
Terrestrial digital radio processor
Rev. 03 — 15 September 2010
Product short data sheet
1. General description
The SAF3560 is a digital radio processor that demodulates and processes digital
terrestrial baseband signals, such as HD Radio signals, into audio signals and digital data
signals.
TUNER1
TUNER2
IF PROCESSING
baseband blend digital
I2S audio
interface
OPTIONAL AUDIO POST
PROCESSING
AND STEREO
AUDIO DAC
SAF3560
SPI2
SERIAL NOR-FLASH
MEMORY
SDRAM
baseband I2S
interface
I2C-bus or SPI1
IF PROCESSING
MICROPROCESSOR
(1) Second input only supported by specific types (see Table 3)
Fig 1. System block diagram
blended
audio (analog)
RENDERING
OF DATA:
LIVE TRAFFIC REPORTS
WEATHER
SPORTS SCORES
STOCK TICKER
001aal423
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Major benefits of terrestrial radio processor systems with SAF3560 are:
• Compatibility with conventional baseband radio reception ICs
• Dramatically improved reception and sound quality
• CD-sound quality without noise, interference and multipath fading for FM
• Providing new data services
• HD Radio reception including audio processing
• Voltage partitioning of I/Os
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RESET_N
XTAL
JTAG
FLASH
SPI1 (host)
SPI2 (FLASH)
SPI3 (tuner)
2 × I2C-bus
GPIO
UART
I/O
CONTROLLER
baseband interface 1
(HD Radio)
baseband interface 2
(HD Radio)
FILTER
AND
SRC
RESET
CGU
CLOCK
JTAG
CONTROLLER
SAF3560
I/O
MUX
internal bus
RADIO
SUB SYSTEM
DUAL
CHANNEL
RADIO
(1 × audio and
data
1 × data only)
AUDIO
SUB SYSTEM
SINGLE
CHANNEL
AUDIO
MEMORY
CONTROLLER
SDRAM
SDRAM
AUDIO
SRC
3 × audio
I2S output
(optional S/PDIF)
BLEND
audio I2S input
001aal422
Fig 2. Block diagram of SAF3560
5 Page 
NXP Semiconductors
SAF3560
Terrestrial digital radio processor
Table 11. Pin description (external host microcontroller interface)
Symbol Pin Type[1] Description
CLKOUT
1
OL clock output; clock source and clock frequency are
programmable through software
RESET_N 2
IZU-H master reset input from host microcontroller (active LOW)
I2C-bus interface (master and slave)
I2C2_DA
9
IOZD-H data acknowledge input and output of the I2C-bus interface 2
I2C2_SCL 7
IOZU serial clock input and output of the I2C-bus interface 2
I2C2_SDA 8
IOZU serial data input and output of the I2C-bus interface 2
I2C1_DA
5
IOZD-H data acknowledge input and output of the I2C-bus interface 1
I2C1_SCL 3
IOZU serial clock input and output of the I2C-bus interface 1
I2C1_SDA 4
IOZU-H serial data input and output of the I2C-bus interface 1
SPI1 interface
SPI1_SCLK 12
IZU-H serial clock input of first SPI interface
SPI1_SI
11
IZU-H slave input of first SPI interface
SPI1_SO 10
OL slave output of first SPI interface
SPI1_SS_N 13
IZU-H slave select input of first SPI interface (active LOW)
UART interface
UART_CTS 29
IZU UART clear-to-send signal input
UART_RD 25
IZU UART receive data input
UART_RTS 26
OH UART ready-to-send signal output
UART_TD 24
OH UART transmit data output
[1] Table 15 defines the pin type.
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Table 12.
Symbol
TCK
TDI
TDO
TMS
TRST_N
Pin description (JTAG interface)
Pin Type[1] Description
132 IZU test clock input
135 IZU test serial data input
136 OL
test serial data output
133 IZU test mode select input
131 IZU test reset input; drive LOW for normal operating
[1] Table 15 defines the pin type.
Table 13.
Symbol
XTALI
XTALO
Pin description (crystal oscillator)
Pin Type[1] Description
141 AI
crystal oscillator analog input
142 AO
crystal oscillator analog output
[1] Table 15 defines the pin type.
Table 14.
Symbol
i.c.
Pin description (internally connected pins)
Pin Type Description
41, -
43 to 54
internally connected; leave open
SAF3560_SDS
Product short data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 15 September 2010
© NXP B.V. 2010. All rights reserved.
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