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PDF SC16C852SV Data sheet ( Hoja de datos )
| Número de pieza | SC16C852SV | |
| Descripción | low power dual channel Universal Asynchronous Receiver and Transmitter (UART) used | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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SC16C852SV
1.8 V dual UART, 20 Mbit/s (max.) with 128-byte FIFOs,
infrared (IrDA), and XScale VLIO bus interface
Rev. 01 — 23 September 2008
Product data sheet
1. General description
The SC16C852SV is a 1.8 V, low power dual channel Universal Asynchronous Receiver
and Transmitter (UART) used for serial data communications. Its principal function is to
convert parallel data into serial data and vice versa. The UART can handle serial data
rates up to 20 Mbit/s (4× sampling rate). SC16C852SV can be programmed to operate in
extended mode where additional advanced UART features are available (see
Section 6.2). The SC16C852SV family UART provides enhanced UART functions with
128-byte FIFOs, modem control interface and IrDA encoder/decoder. On-board status
registers provide the user with error indications and operational status. System interrupts
and modem control features may be tailored by software to meet specific user
requirements. An internal loopback capability allows on-board diagnostics. Independent
programmable baud rate generators are provided to select transmit and receive baud
rates.
The SC16C852SV with Intel XScale processor VLIO interface operates at 1.8 V and is
available in the TFBGA36 package.
2. Features
www.DataSheet4U.net
I Dual channel high performance UART
I 1.8 V operation
I Advanced package: TFBGA36
I Up to 20 Mbit/s data rate (4× sampling) at 1.8 V
I Programmable sampling rate: 16×, 8×, 4×
I 128-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
I 128-byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
I 128 programmable Receive and Transmit FIFO interrupt trigger levels
I 128 Receive and Transmit FIFO reporting levels (level counters)
I Automatic software (Xon/Xoff) and hardware (RTS/CTS or DTR/DSR) flow control
I Programmable Xon/Xoff characters
I 128 programmable hardware and software trigger levels
I Automatic 9-bit mode (RS-485) address detection
I Automatic RS-485 driver turn-around with programmable delay
I Dual channel concurrent write
I UART software reset
I High resolution clock prescaler, from 0 to 15 with granularity of 1⁄16 to allow
non-standard UART clock to be used
1 page  
NXP Semiconductors
SC16C852SV
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
www.DataSheet4U.net
Table 2. Pin description …continued
Symbol Pin Type Description
CS
E2 I
Chip Select (active LOW). This pin enables the data transfers
between the host and the SC16C852SV for the addressed channel.
Individual channel selection is done with address A6. When A6 is 0
channel A is selected, and when A6 is 1 channel B is selected.
CTSA
CTSB
A6 I
F6
Clear to Send (active LOW). These inputs are associated with
individual UART channels, A through B. A logic 0 on the CTS pin
indicates the modem or data set is ready to accept transmit data from
the SC16C852SV. Status can be tested by reading MSR[4].
DSRA
DSRB
A5 I
E4
Data Set Ready (active LOW). These inputs are associated with
individual UART channels, A through B. A logic 0 on this pin indicates
the modem or data set is powered-on and is ready for data exchange
with the UART. Status can be tested by reading MSR[5].
DTRA
DTRB
C5 O
B6
Data Terminal Ready (active LOW). These outputs are associated
with individual UART channels, A through B. A logic 0 on this pin
indicates that the SC16C852SV is powered-on and ready. This pin
can be controlled via the Modem Control Register. Writing a logic 1 to
MCR[0] will set the DTR output to logic 0, enabling the modem. This
pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset.
INTA
D5 O
Channel A interrupt output. The output state is defined by the user
through the software setting of MCR[3]. INTA is set to the active
mode when MCR[3] is set to a logic 1. INTA is set to the 3-state mode
when MCR[3] is set to a logic 0. See Table 19.
INTB
D6 O
Channel B interrupt output. The output state is defined by the user
through the software setting of MCR[3]. INTB is set to the active
mode when MCR[3] is set to a logic 1. INTB is set to the 3-state
mode when MCR[3] is set to a logic 0. See Table 19.
IOR F4 I Read strobe (active LOW). A HIGH to LOW transition on this signal
starts the read cycle. The SC16C852SV reads a byte from the
internal register and puts the byte on the data bus for the host to
retrieve.
IOW E3 I
Write strobe (active LOW). A HIGH to LOW transition on this signal
starts the write cycle, and a LOW to HIGH transition transfers the
data on the data bus to the internal register.
LLA E6 I Latch Lower Address (active LOW). A logic LOW on this pin puts
the VLIO interface in the address phase of the transaction, where the
lower 8 bits of the VLIO (specifying the UART register and the
channel address) are loaded into the address latch of the device
through the AD7 to AD0 bus. A logic HIGH puts the VLIO interface in
the data phase where data can are transferred between the host and
the UART.
LOWPWR F1 I
Low Power. When asserted (active HIGH), the device immediately
goes into low power mode. The oscillator is shut-off and some host
interface pins are isolated from the host’s bus to reduce power
consumption. The device only returns to normal mode when the
LOWPWR pin is de-asserted. On the negative edge of a de-asserting
LOWPWR signal, the device is automatically reset and all registers
return to their default reset states. This pin has an internal pull-down
resistor, therefore, it can be left unconnected.
SC16C852SV_1
Product data sheet
Rev. 01 — 23 September 2008
© NXP B.V. 2008. All rights reserved.
5 of 48
5 Page 
NXP Semiconductors
SC16C852SV
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
www.DataSheet4U.net
Under the above described flow control mechanisms, flow control characters are not
placed (stacked) in the receive FIFO. When using software flow control, the Xon/Xoff
characters cannot be used for data transfer.
In the event that the receive buffer is overfilling, the SC16C852SV automatically sends an
Xoff character (when enabled) via the serial TX output to the remote UART. The
SC16C852SV sends the Xoff1/Xoff2 characters as soon as the number of received data
in the receive FIFO passes the programmed trigger level. To clear this condition, the
SC16C852SV will transmit the programmed Xon1/Xon2 characters as soon as the
number of characters in the receive FIFO drops below the programmed trigger level.
6.7 Special character detect
A special character detect feature is provided to detect an 8-bit character when EFR[5] is
set. When an 8-bit character is detected, it will be placed on the user-accessible data
stack along with normal incoming RXA/RXB data. This condition is selected in conjunction
with EFR[3:0] (see Table 24). Note that software flow control should be turned off when
using this special mode by setting EFR[3:0] to all zeroes.
The SC16C852SV compares each incoming receive character with Xoff2 data. If a match
occurs, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate
detection of a special character. Although Table 7 “SC16C852SV internal registers” shows
Xon-1, Xon-2, Xoff-1, Xoff-2 with eight bits of character information, the actual number of
bits is dependent on the programmed word length. Line Control Register bits LCR[1:0]
define the number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word
length selected by LCR[1:0] also determine the number of bits that will be used for the
special character comparison. Bit 0 in the Xon-1, Xon-2, Xoff-1, Xoff-2 registers
corresponds with the LSB bit for the received character.
6.8 Interrupt priority and time-out interrupts
The interrupts are enabled by IER[7:0]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C852SV
will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to
continuing operations. The ISR indicates the current singular highest priority interrupt
only. A condition can exist where a higher priority interrupt masks the lower priority
interrupt(s) (see Table 12). Only after servicing the higher pending interrupt will the lower
priority interrupt(s) be reflected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
Receive Data Ready and Receive Time Out have the same interrupt priority (when
enabled by IER[0]), and it is important to serve these interrupts correctly. The receiver
issues an interrupt after the number of characters have reached the programmed trigger
level. In this case, the SC16C852SV FIFO may hold more characters than the
programmed trigger level. Following the removal of a data byte, the user should re-check
LSR[0] to see if there are any additional characters. A Receive Time Out will not occur if
the receive FIFO is empty. The time-out counter is reset at the center of each stop bit
received or each time the Receive Holding Register (RHR) is read. The actual time-out
value is 4 character time, including data information length, start bit, parity bit, and the
size of stop bit, that is, 1×, 1.5×, or 2× bit times.
SC16C852SV_1
Product data sheet
Rev. 01 — 23 September 2008
© NXP B.V. 2008. All rights reserved.
11 of 48
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