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PDF HD64F36109 Data sheet ( Hoja de datos )
| Número de pieza | HD64F36109 | |
| Descripción | 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Tiny Series | |
| Fabricantes | Renesas Technology | |
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REJ09B0240-0150
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8/36109Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8 Family / H8/300H Tiny Series
H8/36109F
HD64F36109
HD64F36109G
Rev.1.50
Revision Date: Sep. 18, 2007
1 page  
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 1.50 Sep. 18, 2007 Page v of xxxiv
5 Page 
5.6 Subclock Generator.............................................................................................................. 86
5.6.1 Connecting 32.768-kHz Crystal Resonator............................................................. 86
5.6.2 Pin Connection when not Using Subclock.............................................................. 87
5.7 Prescaler............................................................................................................................... 87
5.7.1 Prescaler S .............................................................................................................. 87
5.7.2 Prescaler W............................................................................................................. 87
5.8 Usage Notes ......................................................................................................................... 88
5.8.1 Note on Resonators................................................................................................. 88
5.8.2 Notes on Board Design ........................................................................................... 88
Section 6 Power-Down Modes ............................................................................89
6.1 Register Descriptions ........................................................................................................... 90
6.1.1 System Control Register 1 (SYSCR1) .................................................................... 90
6.1.2 System Control Register 2 (SYSCR2) .................................................................... 93
6.1.3 System Control Register 3 (SYSCR3) .................................................................... 94
6.1.4 Module Standby Control Register 1 (MSTCR1) .................................................... 94
6.1.5 Module Standby Control Register 2 (MSTCR2) .................................................... 95
6.1.6 Module Standby Control Register 4 (MSTCR4) .................................................... 96
6.2 Mode Transitions and States of LSI..................................................................................... 97
6.2.1 Sleep Mode ........................................................................................................... 100
6.2.2 Standby Mode ....................................................................................................... 100
6.2.3 Subsleep Mode...................................................................................................... 101
6.2.4 Subactive Mode .................................................................................................... 101
6.3 Operating Frequency in Active Mode................................................................................ 101
6.4 Direct Transition ................................................................................................................ 102
6.4.1 Direct Transition from Active Mode to Subactive Mode ..................................... 102
6.4.2 Direct Transition from Subactive Mode to Active Mode ..................................... 103
6.5 Module Standby Function.................................................................................................. 103
Section 7 ROM ..................................................................................................105
7.1 Block Configuration........................................................................................................... 106
7.2 Register Descriptions ......................................................................................................... 107
7.2.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 107
7.2.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 108
7.2.3 Erase Block Register 1 (EBR1) ............................................................................ 109
7.2.4 Flash Memory Power Control Register (FLPWCR) ............................................. 110
7.2.5 Flash Memory Enable Register (FENR) ............................................................... 110
7.3 On-Board Programming Modes......................................................................................... 111
7.3.1 Boot Mode ............................................................................................................ 111
7.3.2 Programming/Erasing in User Programming Mode.............................................. 114
Rev. 1.50 Sep. 18, 2007 Page xi of xxxiv
11 Page | ||
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