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PDF W83627SF Data sheet ( Hoja de datos )
| Número de pieza | W83627SF | |
| Descripción | WINBOND I/O | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W83627SF
www.DataSheet4U.net
W83627SF
WINBOND I/O
Publication Release Date: May 31, 2005
- 1 - Revision A1
1 page  
W83627SF
13.8 Smart Card Status Register (SCSR, at "base address + 5") ............................................ 78
13.9 Extended Control Register (ECR, at "base address + 7") ................................................ 79
13.10 Baud rate divisor Latch High and Baud rate divisor Latch Low (BHL and BLL at "base
address + 1" and "base address + 0" respectively when BDLAB = 1) ............................ 80
14. SERIAL IRQ ................................................................................................................................. 81
14.1 Start Frame ........................................................................................................................ 81
14.2 IRQ/Data Frame ................................................................................................................. 81
14.3 Stop Frame......................................................................................................................... 82
15. CONFIGURATION REGISTER ................................................................................................... 83
15.1 Chip (Global) Control Register ........................................................................................... 83
15.2 Logical Device 0 (FDC) ...................................................................................................... 89
15.3 Logical Device 1 (Parallel Port).......................................................................................... 92
15.4 Logical Device 2 (UART A) ................................................................................................ 93
15.5 Logical Device 3 (UART B) ................................................................................................ 93
15.6 Logical Device 5 (KBC) ...................................................................................................... 95
15.7 Logical Device 6 (CIR) ....................................................................................................... 96
15.8 Logical Device 7 (Game Port and MIDI Port and GPIO Port 1)........................................ 96
15.9 Logical Device 8 (GPIO Port 2).......................................................................................... 97
15.10 Logical Device 9 (GPIO Port 3,4 are powered by standby source VSB)........................... 99
15.11 Logical Device A (ACPI)................................................................................................... 100
15.12 Logical Device B (Smart Card interface).......................................................................... 107
15.13 Logical Device C (GPIO Port 5,6,7 This power of the Ports is Source VCC) .................. 107
16. SPECIFICATIONS ..................................................................................................................... 109
16.1 Absolute Maximum Ratings ............................................................................................. 109
16.2 DC CHARACTERISTICS ................................................................................................. 109
17. APPLICATION CIRCUITS ......................................................................................................... 112
17.1 Parallel Port Extension FDD ............................................................................................ 112
17.2 Parallel Port Extension 2FDD .......................................................................................... 113
17.3 Four FDD Mode................................................................................................................ 113
18. ORDERING INSTRUCTION ...................................................................................................... 114
19. HOW TO READ THE TOP MARKING....................................................................................... 114
20. PACKAGE DIMENSIONS .......................................................................................................... 115
21. REVISION HISTORY ................................................................................................................. 116
Publication Release Date: May 31, 2005
- 5 - Revision A1
5 Page 
W83627SF
4. PIN DESCRIPTION
Note: Please refer to Section 16.2 DC CHARACTERISTICS for details.
I/O8t - TTL level bi-directional pin with 8 mA source-sink capability
I/O12t - TTL level bi-directional pin with 12 mA source-sink capability
I/O12tp3 - 3.3V TTL level bi-directional pin with 12 mA source-sink capability
I/OD12t - TTL level bi-directional pin open drain output with 12 mA sink capability
I/OD16t - TTL level bi-directional pin open drain output with 16 mA sink capability
I/OD24 - TTL level bi-directional pin open drain output with 24A sink capability
OUT2 - Output pin with 2 mA source-sink capability
OUT12 - Output pin with 12 mA source-sink capability
O12tp3 - 3.3V output pin with 12 mA source-sink capability
OD12 - Open-drain output pin with 12 mA sink capability
OD24 - Open-drain output pin with 24 mA sink capability
INcs - CMOS level Schmitt-trigger input pin
INt - TTL level input pin
INtd - TTL level input pin with internal pull down resistor
INts - TTL level Schmitt-trigger input pin
INtsp3 - 3.3V TTL level Schmitt-trigger input pin
4.1 LPC Interface
SYMBOL
CLKIN
PME#
PCICLK
LDRQ#
SERIRQ
LAD[3:0]
LFRAME#
LRESET#
SUSCLKIN
PIN
18
19
21
22
23
24-27
29
30
75
I/O
INt
OD12
INtsp3
O12tp3
I/OD12t
I/O12tp3
INtsp3
INtsp3
INts
FUNCTION
System clock input. According to the input frequency 24MHz or
48MHz, it is selectable through register. Default is 24MHz input.
Generated PME event.
PCI clock input.
Encoded DMA Request signal.
Serial IRQ input/Output.
These signal lines communicate address, control, and data
information over the LPC bus between a host and a peripheral.
Indicates start of a new cycle or termination of a broken cycle.
Reset signal. It can connect to PCIRST# signal on the host.
32khz clock input, for CIR only.
- 11 -
Publication Release Date: May 31, 2005
Revision A1
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet W83627SF.PDF ] | |
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