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PDF NBXHGA017 Data sheet ( Hoja de datos )
| Número de pieza | NBXHGA017 | |
| Descripción | LVPECL Clock Oscillator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NBXHGA017
2.5/3.3 V, 156.25 MHz
LVPECL Clock Oscillator
The NBXHGA017, single frequency, crystal oscillator (XO) is
designed to meet today’s requirements for 2.5/3.3 V LVPECL clock
generation applications. The device uses a high Q fundamental crystal
and Phase Lock Loop (PLL) multiplier to provide 156.25 MHz, ultra
low jitter and phase noise LVPECL differential output.
This device is a member of ON Semiconductor’s PureEdget clock
family that provides accurate and precision clock solutions.
Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape
and reel in quantities of 100 and 1,000.
Features
• LVPECL Differential Output
• Uses High Q Fundamental Mode Crystal and PLL Multiplier
• Ultra Low Jitter and Phase Noise − 0.5 ps (12 kHz − 20 MHz)
• Output Frequency − 156.25 MHz
• Hermetically Sealed Ceramic SMD Package
• RoHS Compliant
• Operating Range: 2.5 V ±5% or 3.3 V ±10%
• Total Frequency Stability − $50 PPM
• This is a Pb−Free Device
Applications
• Networking
• Storage
• Wireless Radio Communications
VDD
6
CLK CLK
54
http://onsemi.com
MARKING DIAGRAM
6 PIN CLCC
LN SUFFIX
CASE 848AB
NBXHGA017
156.2500
AAWLYYWWG
NBXHGA017= NBXHGA017 (±50 PPM)
156.2500 = Output Frequency (MHz)
AA = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device
Package Shipping†
NBXHGA017LN1TAG CLCC−6 1000 / Tape &
(Pb−Free)
Reel
NBXHGA017LNHTAG CLCC−6 100 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Crystal
PLL
Clock
Multiplier
1 23
OE NC GND
Figure 1. Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2010
www.DatAaSphreile, t240U1.0ne−t Rev. 0
1
Publication Order Number:
NBXHGA017/D
1 page  
NBXHGA01
7
Q
Driver
Device
Q
NBXHGA017
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VDD − 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Temperature (°C)
260
217
temp. 260°C
20 − 40 sec. max.
peak
3°C/sec. max.
ramp−up
175
150 pre−heat
reflow
6°C/sec. max.
cooling
Time
60180 sec.
60150 sec.
Figure 5. Recommended Reflow Soldering Profile
http://onsemi.com
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet NBXHGA017.PDF ] | |
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