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PDF M170E6-L01 Data sheet ( Hoja de datos )
| Número de pieza | M170E6-L01 | |
| Descripción | LCD Module | |
| Fabricantes | CHI MEI | |
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1 page  
DCC No.:14029063
Issued Date: Sep.,24, 2002
Model No.: M170E6 -L01
Tentative
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item
Storage Temperature
Operating Ambient Temperature
Shock (Non-Operating)
Vibration (Non-Operating)
Symbol
TST
TOP
SNOP
VNOP
Min.
(-20)
0
-
-
Value
Max.
(+60)
(+50)
50
1.5
Note (1) Temperature and relative humidity range is shown in the figure below.
Unit Note
ºC (1)
ºC (1), (2)
G (3), (5)
G (4), (5)
(a) 90 %RH Max. (Ta ≦ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The temperature of panel surface should be 0 ºC Min. and 60 ºC Max.
Note (3) 11ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 300 Hz, 10min/cycle,1 times X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough
so that the module would not be twisted or bent by the fixture.
Relative Humidity (%RH)
100
90
80
60
Operating Range
40
20
5 Storage Range
-40 -20
0 20 40
Temperature (ºC)
60 80
5 / 22
The information described in this technical specification is tentative and it is possible to be changed without prior
notice. Please contact CMO ’s representative while your product design is based on this specification. Version 0.1
5 Page 
DCC No.:14029063
Issued Date: Sep.,24, 2002
Model No.: M170E6 -L01
Tentative
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE
Pin Name
1 RXO0-
2 RXO0+
3 RXO1-
4 RXO1+
5 RXO2-
6 RXO2+
7 GND
8 RXOC-
9 RXOC+
10 RXO3-
11 RXO3+
12 RXE0-
13 RXE0+
14 GND
15 RXE1-
16 RXE1+
17 GND
18 RXE2-
19 RXE2+
20 RXEC-
21 RXEC+
22 RXE3-
23 RXE3+
24 GND
25 TEST
26 NC
27 SELLVDS
28 VCC
29 VCC
30 VCC
Description
Negative LVDS differential data input. Channel O0 (odd)
Positive LVDS differential data input. Channel O0 (odd)
Negative LVDS differential data input. Channel O1 (odd)
Positive LVDS differential data input. Channel O1 (odd)
Negative LVDS differential data input. Channel O2 (odd)
Positive LVDS differential data input. Channel O2 (odd)
Ground
Negative LVDS differential clock input. (odd)
Positive LVDS differential clock input. (odd)
Negative LVDS differential data input. Channel O3(odd)
Positive LVDS differential data input. Channel O3 (odd)
Negative LVDS differential data input. Channel E0 (even)
Positive LVDS differential data input. Channel E0 (even)
Ground
Negative LVDS differential data input. Channel E1 (even)
Positive LVDS differential data input. Channel E1 (even)
Ground
Negative LVDS differential data input. Channel E2 (even)
Positive LVDS differential data input. Channel E2 (even)
Negative LVDS differential clock input. (even)
Positive LVDS differential clock input. (even)
Negative LVDS differential data input. Channel E3 (even)
Positive LVDS differential data input. Channel E3 (even)
Ground
Test pin should be tied to ground.
Not connection.
SELLVDS pin should be tied to ground or open.
+5.0V power supply
+5.0V power supply
+5.0V power supply
Note (1) Connector Part No.: TBD
Note (2) The first pixel is odd.
Note (3) Input signal of even and odd clock should be the same timing.
11 / 22
The information described in this technical specification is tentative and it is possible to be changed without prior
notice. Please contact CMO ’s representative while your product design is based on this specification. Version 0.1
11 Page | ||
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