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PDF N141X6-L03 Data sheet ( Hoja de datos )

Número de pieza N141X6-L03
Descripción LCD Module
Fabricantes CHI MEI 
Logotipo CHI MEI Logotipo



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N141X6-L03 pdf
Issued Date: Oct.15.’01
Model No.: N141X6 -L03
Approval
1. GENERAL DESCRIPTION
1.1 OVERVIEW
N141X6- L03 is a 14.1” TFT Liquid Crystal Display module with single CCFL Backlight unit and 20 pins
LVDS interface. This module supports 1024 x 768 XGA mode and can display 262,144 colors. The optimum
viewing angle is at 6 o’clock direction. The inverter module for Backlight is not built in.
1.2 FEATURES
- Thin and light weight and high brightness
- XGA (1024 x 768 pixels) resolution
- DE (Data Enable) only mode
- 3.3V LVDS (Low Voltage Differential Signaling) interface with 1 pixel/clock
1.3 APPLICATION
- TFT LCD Notebook
1.4 GENERAL SPECIFICATI0NS
Item
Active Area
Bezel Opening Area
Driver Element
Pixel Number
Pixel Pitch
Pixel Arrangement
Display Colors
Transmissive Mode
Surface Treatment
Specification
285.7 (H) x 214.3 (V) (14.1” diagonal)
288.9 (H) x 217.5 (V)
a-si TFT active matrix
1024 x R.G.B. x 768
0.279 (H) x 0.279 (V)
RGB vertical stripe
262,144
Normally white
Hard coating (3H), Anti-glare (Haze 25)
Unit
mm
mm
-
pixel
mm
-
color
-
-
Note
(1)
-
-
-
-
-
-
-
1.5 MECHANICAL SPECIFICATIONS
Item
Horizontal(H)
Module Size Vertical(V)
Depth(D)
Weight
Min.
298.0
226.0
-
-
Typ.
298.5
226.5
5.2
470
Max.
299.0
227.0
5.5
485
Unit Note
mm
mm (1)
mm
g-
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
5 / 22
Version 3.2

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N141X6-L03 arduino
Issued Date: Oct.15.’01
Model No.: N141X6 -L03
Approval
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE
Pin Symbol
Description
1 Vcc Power Supply +3.3 V
2 Vcc Power Supply +3.3 V
3 Vss Ground
4 Vss Ground
5 Rxin0- LVDS Differential Data Input
6 Rxin0+ LVDS Differential Data Input
7 Vss Ground
8 Rxin1- LVDS Differential Data Input
9 Rxin1+ LVDS Differential Data Input
10 Vss Ground
11 Rxin2- LVDS Differential Data Input
12 Rxin2+ LVDS Differential Data Input
13 Vss Ground
14 CLK- LVDS Clock Data Input
15 CLK+ LVDS Clock Data Input
16 Vss Ground
17 NC Non-Connection
18 NC Non-Connection
19 Vss Ground
20 Vss Ground
Note (1) Connector Part No.: JAE-FI-XB20S-HF10 or equivalent
Note (2) User’s connector Part No: JAE-FI-X20M or equivalent
Note (3) The first pixel is even.
Polarity
Negative
Positive
Negative
Positive
Negative
Positive
Negative
Positive
Remark
-
-
-
-
R0~R5,G0
-
G1~G5,B0,B1
-
B2~B5,DE,Hsync,Vsync
-
LVDS Level
-
-
-
-
-
5.2 BACKLIGHT UNIT
Pin
Symbol
Description
1 HV High Voltage
2 LV Ground
Note (1) Connector Part No.: JST-BHSR-02VS-1 or equivalent
Note (2) User’s connector Part No.: JST-SM02B-BHSS-1-TB or equivalent
Color
White
Black
5.3 TIMING DIAGRAM OF LVDS INPUT SIGNAL
CLK+
Rxin2
T/7
IN20
IN19
IN18
IN17
IN16
DE
Vsync
Hsync
B5
B4
Rxin1
IN13
IN12
IN11
IN10
IN9
B1 B0 G5 G4 G3
Rxin0
IN6
IN5
IN4
IN3
IN2
G0 R5 R4 R3 R2
Signal for 1 DCLK Cycle (T)
IN15
B3
IN8
G2
IN1
R1
IN14
B2
IN7
G1
IN0
R0
11 / 22
Version 3.2

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