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H5MS2532JFR PDF даташит

Спецификация H5MS2532JFR изготовлена ​​​​«Hynix Semiconductor» и имеет функцию, называемую «256Mb (8Mx32bit) Mobile DDR SDRAM».

Детали детали

Номер произв H5MS2532JFR
Описание 256Mb (8Mx32bit) Mobile DDR SDRAM
Производители Hynix Semiconductor
логотип Hynix Semiconductor логотип 

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H5MS2532JFR Даташит, Описание, Даташиты
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256Mbit MOBILE DDR SDRAM based on 2M x 4Bank x32 I/O
Specification of
256Mb (8Mx32bit) Mobile DDR SDRAM
Memory Cell Array
- Organized as 4banks of 2,097,152 x32
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.2 / Apr. 2009
1









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H5MS2532JFR Даташит, Описание, Даташиты
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256Mbit MOBILE DDR SDRAM based on 2M x 4Bank x32 I/O
Document Title
256MBit (4Bank x 2M x 32bits) MOBILE DDR SDRAM
Revision History
Revision No.
History
0.1 Initial Draft
0.2 IDD Specification updated
1.0 The final version
1.1 Correct Part No. (page 3)
1.2 Insert DDR370 DC/AC Characteristics
Draft Date
May 2008
May 2008
Nov. 2008
Mar. 2009
Apr. 2009
Remark
Preliminary
Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.2 / Apr. 2009
2









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H5MS2532JFR Даташит, Описание, Даташиты
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Mobile DDR SDRAM 256Mbit (8M x 32bit)
H5MS2622JFR Series
H5MS2532JFR Series
FEATURES SUMMARY
Mobile DDR SDRAM
- Double data rate architecture: two data transfer per
clock cycle
Mobile DDR SDRAM INTERFACE
- x32 bus width
- Multiplexed Address (Row address and Column ad-
dress)
SUPPLY VOLTAGE
- 1.8V device: VDD and VDDQ = 1.7V to 1.95V
MEMORY CELL ARRAY
- 256Mbit (x32 device) = 2M x 4Bank x 32 I/O
DATA STROBE
- x32 device: DQS0 ~ DQS3
- Bidirectional, data strobe (DQS) is transmitted and re-
ceived with data, to be used in capturing data at the
receiver
- Data and data mask referenced to both edges of DQS
LOW POWER FEATURES
- PASR (Partial Array Self Refresh)
- AUTO TCSR (Temperature Compensated Self Refresh)
- DS (Drive Strength)
- DPD (Deep Power Down): DPD is an optional feature,
so please contact Hynix office for the DPD feature
INPUT CLOCK
- Differential clock inputs (CK, CK)
Data MASK
- DM0 ~ DM3: Input mask signals for write data
- DM masks write data-in at the both rising and
falling edges of the data strobe
MODE RERISTER SET, EXTENDED MODE REGIS-
TER SET and STATUS REGISTER READ
- Keep to the JEDEC Standard regulation
(Low Power DDR SDRAM)
CAS LATENCY
- Programmable CAS latency 2 or 3 supported
BURST LENGTH
- Programmable burst length 2 / 4 / 8 with both sequen-
tial and interleave mode
AUTO PRECHARGE
- Option for each burst access
AUTO REFRESH AND SELF REFRESH MODE
CLOCK STOP MODE
- Clock stop mode is a feature supported by Mobile DDR
SDRAM.
- Keep to the JEDEC Standard regulation
INITIALIZING THE MOBILE DDR SDRAM
- Occurring at device power up or interruption of device
power
PACKAGE
- H5MS262(53)2JFR: 90 Ball FBGA, Lead & Halogen free
ADDRESS TABLE
Part Number Page Size
Row
Address
H5MS2622JFR 2KByte A0 ~ A11
H5MS2532JFR 1KByte A0 ~ A12
Column
Address
A0 ~ A8
A0 ~ A7
Rev 1.2 / Apr. 2009
3










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Номер в каталогеОписаниеПроизводители
H5MS2532JFR256Mb (8Mx32bit) Mobile DDR SDRAMHynix Semiconductor
Hynix Semiconductor

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