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PDF HMP525P7FFP4C-Y5 Data sheet ( Hoja de datos )
| Número de pieza | HMP525P7FFP4C-Y5 | |
| Descripción | 240pin Registered DDR2 SDRAM DIMMs | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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240pin Registered DDR2 SDRAM DIMMs based on 512 Mb F ver.
This Hynix registered Dual In-Line Memory Module (DIMM) series consists of 512Mb F ver. DDR2 SDRAMs in Fine Ball
Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 512Mb F ver. based Registered DDR2 DIMM
series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable
for easy interchange and addition.
ORDERING INFORMATION
Part Name
HMP564P7FFP8C-Y5
HMP512R7FFP4C-E3
HMP512P7FFP4C-Y5
HMP525R7FFP4C-E3
HMP525P7FFP4C-Y5
Density
Org.
512MB
1GB
1GB
2GB
2GB
64Mx72
128Mx72
128Mx72
256Mx72
256Mx72
Component Configuration
Ranks
Parity
Support
64Mx8(H5PS5182FFP)*9
128Mx4(H5PS5142FFP)*18
128Mx4(H5PS5142FFP)*18
128Mx4(H5PS5142FFP)*36
128Mx4(H5PS5142FFP)*36
1
1
1
2
2
O
X
O
X
O
Note:
1. “P” of part number[7th digit] stands for Parity Registered DIMM.
2. “P” of part number[11th digit] stands for Lead free products.
SPEED GRADE & KEY PARAMETERS
E3 (DDR2-400) C4 (DDR2-533) Y5 (DDR2-667) S6 (DDR2-800) S5 (DDR2-800)
Speed@CL3
Speed@CL4
Speed@CL5
Speed@CL6
CL-tRCD-tRP
400
400
-
-
3-3-3
400
533
-
-
4-4-4
400
533
667
-
5-5-5
400
533
-
800
6-6-6
400
533
800
-
5-5-5
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1 / May. 2008
1
1 page  
www.DataSheet4U.net
1240pin Registered DDR2 SDRAM DIMMs
PIN ASSIGNMENT
Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name
1
VREF
41
VSS
81 DQ33 121
VSS
161
CB4
201
VSS
2 VSS 42 CB0 82 VSS 122 DQ4 162 CB5 202 DM4/DQS13
3 DQ0 43 CB1 83 DQS4 123 DQ5 163 VSS 203 DQS13
4 DQ1 44 VSS 84 DQS4 124 VSS 164 DM8,DQS17 204 VSS
5
VSS
45 DQS8 85
VSS
125 DM0/DQS9 165
DQS17
205
DQ38
6
DQS0
46
DQS8
86
DQ34
126
DQS9
166
VSS
206 DQ39
7
DQS0
47
VSS
87 DQ35 127
VSS
167
CB6
207
VSS
8 VSS 48 CB2 88 VSS 128 DQ6 168 CB7 208 DQ44
9 DQ2 49 CB3 89 DQ40 129 DQ7 169 VSS 209 DQ45
10 DQ3 50 VSS 90 DQ41 130 VSS 170 VDDQ 210 VSS
11 VSS 51 VDDQ 91 VSS 131 DQ12 171 NC,CKE1 211 DM5/DQS14
12
DQ8
52
CKE0
92
DQS5
132
DQ13
172
VDD
212 DQS14
13 DQ9 53 VDD 93 DQS5 133 VSS 173 A15,NC 213 VSS
14
VSS
54 BA2,NC 94
VSS
134 DM1/DQS10 174
A14,NC
214
DQ46
15
DQS1
55 NC,Err_Out 95
DQ42
135 DQS10
175
VDDQ
215
DQ47
16
DQS1
56 VDDQ 96
DQ43
136
VSS
176
A12
216
VSS
17 VSS 57 A11 97 VSS 137 RFU 177 A9 217 DQ52
18 RESET 58 A7 98 DQ48 138 RFU 178 VDD 218 DQ53
19 NC 59 VDD 99 DQ49 139 VSS 179 A8 219 VSS
20 VSS 60 A5 100 VSS 140 DQ14 180 A6 220 RFU
21 DQ10 61
A4 101 SA2 141 DQ15 181 VDDQ 221 RFU
22
DQ11
62
VDDQ
102 NC(TEST) 142
VSS
182
A3
222 VSS
23 VSS 63 A2 103 VSS 143 DQ20 183 A1 223 DM6/DQS15
24 DQ16 64 VDD 104 DQS6 144 DQ21 184 VDD 224 NC,DQS15
25 DQ17
Key
105 DQS6 145
VSS
Key 225 VSS
26 VSS 65 VSS 106 VSS 146 DM2/DQS11 185 CK0 226 DQ54
27 DQS2 66 VSS 107 DQ50 147 DQS11 186 CK0 227 DQ55
28 DQS2 67 VDD 108 DQ51 148 VSS 187 VDD 228 VSS
29 VSS 68 NC,Err_Out 109 VSS 149 DQ22 188 A0 229 DQ60
30 DQ18 69 VDD 110 DQ56 150 DQ23 189 VDD 230 DQ61
31
DQ19
70 A10/AP 111
DQ57
151
VSS
190
BA1
231
VSS
32 VSS 71 BA0 112 VSS 152 DQ28 191 VDDQ 232 DM7/DQS16
33
DQ24
72
VDDQ
113
DQS7
153
DQ29
192
RAS
233 NC,DQS16
34 DQ25 73 WE 114 DQS7 154 VSS 193 S0 234 VSS
35 VSS 74 CAS 115 VSS 155 DM3/DQS12 194 VDDQ 235 DQ62
36
DQS3
75
VDDQ
116
DQ58
156 DQS12
195
ODT0
236
DQ63
37
DQS3
76 NC, S1 117
DQ59
157
VSS
196 A13,NC 237
VSS
38 VSS 77 NC, ODT1 118 VSS 158 DQ30 197 VDD 238 VDDSPD
39
DQ26
78
VDDQ
119
SDA
159 DQ31
198
VSS
239
SA0
40 DQ27 79 VSS 120 SCL 160 VSS 199 DQ36 240 SA1
80 DQ32
200 DQ37
NC= No Connect, RFU= Reserved for Future Use.
Note:
1. RESET(Pin 18) is connected to both OE of PLL and Reset of register.
2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity.
3. The Test pin(Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules(DIMMs)
Rev. 0.1 / May. 2008
5
5 Page 
www.DataSheet4U.net
1240pin Registered DDR2 SDRAM DIMMs
Differential Input AC logic Level
Symbol
Parameter
Min.
Max.
Units Note
VID (ac)
ac differential input voltage
0.5
VDDQ + 0.6
V1
VIX (ac)
ac differential cross point voltage
0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175
V
2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,
LDQS, UDQS and UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as
CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The mini-
mum value is equal to VIH(DC) - VIL(DC).
VTR
VCP
VDDQ
VID
Crossing point
VIX or VOX
VSSQ
< Differential signal levels >
Notes:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal
(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).
The minimum value is equal to V IH(AC) - VIL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to
track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.
DIFFERENTIAL AC OUTPUT PARAMETERS
Symbol
VOX (ac)
Parameter
ac differential cross point voltage
Min.
0.5 * VDDQ - 0.125
Max.
0.5 * VDDQ + 0.125
Units
V
Note
1
Note:
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to
track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
Rev. 0.1 / May. 2008
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet HMP525P7FFP4C-Y5.PDF ] | |
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