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Спецификация 845G изготовлена ​​​​«Intel Corporation» и имеет функцию, называемую «Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub».

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Номер произв 845G
Описание Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub
Производители Intel Corporation
логотип Intel Corporation логотип 

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Intel® 845G/845GL/845GV Chipset
Datasheet
Intel® 82845G/82845GL/82845GV Graphics and Memory Controller
Hub (GMCH)
October 2002
Document Number: 290746-002
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel 845G/845GL/845GV chipsets may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.
Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
Intel, Pentium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other
countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2002, Intel Corporation
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Contents
1 Introduction...........................................................................................................13
1.1 Terminology ...................................................................................................13
1.2 Related Documents .......................................................................................14
1.3 Intel® 845G Chipset System Overview ..........................................................15
1.4 Intel® 82845G GMCH Overview....................................................................17
1.4.1 Host Interface....................................................................................17
1.4.2 System Memory Interface .................................................................17
1.4.3 Hub Interface ....................................................................................17
1.4.4 Multiplexed AGP and Intel® DVO Port Interface ...............................18
1.4.5 Graphics Overview............................................................................18
1.4.6 Display Interfaces .............................................................................19
2 Signal Description ..............................................................................................21
2.1 Host Interface Signals....................................................................................23
2.2 Memory Interface ...........................................................................................25
2.2.1 DDR SDRAM Interface .....................................................................25
2.2.2 SDR SDRAM Interface .....................................................................26
2.3 Hub Interface .................................................................................................28
2.4 AGP Interface Signals....................................................................................29
2.4.1 AGP Addressing Signals...................................................................29
2.4.2 AGP Flow Control Signals ................................................................29
2.4.3 AGP Status Signals ..........................................................................30
2.4.4 AGP Strobes .....................................................................................30
2.4.5 PCI Signals–AGP Semantics............................................................31
2.4.6 PCI Pins during PCI Transactions on AGP Interface ........................32
2.5 Multiplexed Intel® DVO Device Signal Interfaces ..........................................32
2.5.1 Intel® DVO Signal Name to AGP Signal Name Pin Mapping............34
2.6 Analog Display ...............................................................................................35
2.7 Clocks, Reset, and Miscellaneous Signals ....................................................36
2.8 RCOMP, VREF, VSWING Signals.................................................................36
2.9 Power and Ground Signals ............................................................................37
2.10 Functional Straps ...........................................................................................38
2.11 GMCH Sequencing Requirements.................................................................38
2.12 Reset States ..................................................................................................39
2.12.1 Full and Warm Reset States .............................................................39
3 Register Description..........................................................................................41
3.1 Register Terminology.....................................................................................41
3.2 Platform Configuration ...................................................................................42
3.3 Routing Configuration Accesses....................................................................43
3.3.1 Standard PCI Bus Configuration Mechanism ...................................44
3.3.2 PCI Bus #0 Configuration Mechanism ..............................................44
3.3.3 Primary PCI and Downstream Configuration Mechanism.................44
3.3.4 AGP/PCI_B Bus Configuration Mechanism ......................................44
3.4 I/O Mapped Registers ....................................................................................46
3.4.1 CONFIG_ADDRESS—Configuration Address Register ...................46
3.4.2 CONFIG_DATA—Configuration Data Register ................................47
3.5 Intel® GMCH Internal Device Registers .........................................................48
Intel® 82845G/82845GL/82845GV GMCH Datasheet
3
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