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PDF NL3224BC35-21 Data sheet ( Hoja de datos )
| Número de pieza | NL3224BC35-21 | |
| Descripción | Display Module | |
| Fabricantes | NEC | |
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TFT COLOR LCD MODULE
NL3224BC35-21
13.9cm (5.5 Type)
QVGA
DATA SHEET
DOD-PD-0638 (1st edition)
All information is subject to change without
notice. Please confirm the sales representative
before starting to design your system.
Document Number: DOD-PD-0638 (1st edition)
Published date: September 2004 CP(N)
1 © NEC LCD Technologies, Ltd.
2004, All rights reserved.
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NL3224BC35-21
2. GENERAL SPECIFICATIONS
Display area
Diagonal size of display
Drive system
Display color
Pixel
Pixel arrangement
Dot pitch
Pixel pitch
Module size
Weight
Contrast ratio
Viewing angle
Designed viewing direction
Polarizer surface
Polarizer pencil-hardness
Color gamut
Response time
Luminance
Signal system
Power supply voltage
Backlight
Power consumption
111.4 (H) × 83.5 (V) mm
13.9 cm (5.5 inches)
a-Si TFT active matrix
262,144 colors
320 (H) × 240 (V) pixels
RGB (Red dot, Green dot, Blue dot) vertical stripe
0.1160 (H) × 0.3480 (V) mm
0.3480 (H) × 0.3480 (V) mm
134.0 (W) × 104.5 (H) × 12.5 (D) mm (typ.)
210 g (typ.)
400:1 (typ.)
At the contrast ratio ≥10:1
• Horizontal: Right side 55° (typ.), Left side 55° (typ.)
• Vertical: Up side 50° (typ.), Down side 40° (typ.)
At DPSH, DPSV= Open: Normal scan
• Viewing direction without image reversal: down side (6 o'clock)
• Viewing direction with contrast peak: up side (12 o'clock)
• Viewing angle with optimum grayscale (γ=2.2): normal axis
Antiglare
3H (min.) [by JIS K5400]
At LCD panel center
50 % (typ.) [against NTSC color space]
Ton (white 90% → black 10%)
5 ms (typ.)
At IBL= 5.0mArms / lamp
400 cd/m2 (typ.)
6-bit digital signals for data of RGB colors,
Dot clock (CLK), Data enable (DE),
Horizontal synchronous signal (Hsync),
Vertical synchronous signal (Vsync)
LCD panel signal processing board: 3.3V or 5.0V
Edge light type: 2 cold cathode fluorescent lamps
Replaceable parts
• Lamp holder set: Type No. 55LHS13
Recommended inverter (Option)
• Inverter: Type No. 55PW131
At IBL= 5.0mArms / lamp and checkered flag pattern
4.1 W (typ., Power dissipation of the inverter is not included.)
DATA SHEET DOD-PD-0638 (1st edition)
5
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4.4 POWER SUPPLY VOLTAGE SEQUENCE
4.4.1 Sequence for LCD panel signal processing board
VCC 3.0V or 4.75V
Note1
0V
Display and
function signals
Note2
ON
Tr < 20ms
0ms < t < 35ms
VALID period
NL3224BC35-21
OFF
Toff > 200ms
0ms < t < 35ms
Note1: In terms of voltage variation (voltage drop) while VCC rising edge is below 3.0V in "VCC =
3.3V" or 4.75V in "VCC = 5.0V", a protection circuit may work, and then this product may not
work.
Note2: Display signals (CLK, Hsync, Vsync, DE, R0 to R5, G0 to G5, B0 to B5) and function signal
(DPSH, DPSV) must be Low or High-impedance, exclude the VALID period (See above
sequence diagram), in order to avoid that internal circuits is damaged.
If some of display and function signals of this product are cut while this product is working,
even if the signal input to it once again, it might not work normally. If customer stops the
display and function signals, they should be cut VCC.
4.4.2 Sequence for backlight inverter (Option)
Display and
function signals
Note1
Note2
VALID period
VDDB
Note1: These are display and function signals for LCD panel signal processing board.
Note2: The backlight inverter voltage (VDDB) should be inputted within the valid period of display
and function signals, in order to avoid unstable data display.
DATA SHEET DOD-PD-0638 (1st edition)
11
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