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H5TQ2G63DFR-xxC PDF даташит

Спецификация H5TQ2G63DFR-xxC изготовлена ​​​​«Hynix Semiconductor» и имеет функцию, называемую «2Gb DDR3 SDRAM».

Детали детали

Номер произв H5TQ2G63DFR-xxC
Описание 2Gb DDR3 SDRAM
Производители Hynix Semiconductor
логотип Hynix Semiconductor логотип 

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H5TQ2G63DFR-xxC Даташит, Описание, Даташиты
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Preliminary
2Gb DDR3 SDRAM
2Gb DDR3 SDRAM
Lead-Free&Halogen-Free
(RoHS Compliant)
H5TQ2G83DFR-xxC
H5TQ2G63DFR-xxC
H5TQ2G83DFR-xxI
H5TQ2G63DFR-xxI
* Hynix Semiconductor reserves the right to change products or specifications without notice.
Rev. 0.05 / Nov. 2011
1
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H5TQ2G63DFR-xxC Даташит, Описание, Даташиты
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Revision History
Revision No.
0.01
0.02
0.03
0.04
0.05
History
Preliminary version release
Add temperature information in feature
update operation frequency
update IDD 1600,1866,2133
update IDD data
Draft Date
July. 2011
Aug. 2011
Oct. 2011
Nov. 2011
Nov. 2011
Preliminary
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Rev. 0.05 / Nov. 2011
2
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H5TQ2G63DFR-xxC Даташит, Описание, Даташиты
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Preliminary
Description
The H5TQ2G83DFR-xxC, H5TQ2G63DFR-xxC,H5TQ2G83DFR-xxI, H5TQ2G63DFR-xxI are a 2,147,483,648-
bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applica-
tions which requires large memory density and high bandwidth. Hynix 2Gb DDR3 SDRAMs offer fully syn-
chronous operations referenced to both rising and falling edges of the clock. While all addresses and
control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and
Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally
pipelined and 8-bit prefetched to achieve very high bandwidth.
Device Features and Ordering Information
FEATURES
• VDD=VDDQ=1.5V +/- 0.075V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK
transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data,
data strobes and data masks latched on the
rising edges of the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13
and 14 supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 8banks
• Average Refresh Cycle (Tcase 0 oC~95oC)
- 7.8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC
Commercial Temperature( 0oC ~ 85 oC)
Industrial Temperature( -40oC ~ 95 oC)
• Auto Self Refresh supported
• JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre-fetch
* This product in compliance with the RoHS directive.
Rev. 0.05 / Nov. 2011
3
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