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PDF W29GL064C Data sheet ( Hoja de datos )
| Número de pieza | W29GL064C | |
| Descripción | 64M-BIT 3.0-VOLT PARALLEL FLASH MEMORY | |
| Fabricantes | Winbond | |
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W29GL064C
64M-BIT
3.0-VOLT PARALLEL FLASH MEMORY WITH
PAGE MODE
Publication Release Date: August 2, 2013
Revision H
1 page  
W29GL064C
List of Figures
Figure 3-3-1
Figure 3-3-2
Figure 3-3-3
Figure 3-3-4
Figure 4-1
Figure 7-1
Figure 7-2
Figure 7-3
Figure 8-1
Figure 8-2
Figure 8-3
Figure 8-4
Figure 8-5
Figure 8-6
Figure 8-7
Figure 8-8
Figure 8-9
Figure 8-10
Figure 8-11
Figure 8-12
Figure 8-13
Figure 8-14
Figure 8-15
Figure 8-16
Figure 8-17
Figure 8-18
Figure 8-19
Figure 8-20
Figure 8-21
Figure 8-22
Figure 8-23
Figure 8-24
Figure 8-25
Figure 8-26
Figure 8-27
Figure 8-28
Figure 9-1
Figure 9-2
Figure 9-3
Figure 9-4
Figure 10-1
LFBGA64 TOP VIEW (FACE DOWN).......................................................................... 2
56-PIN STANDARD TSOP (TOP VIEW)....................................................................... 2
TFBGA48 TOP VIEW (FACE DOWN) .......................................................................... 2
48-PIN STANDARD TSOP (TOP VIEW)....................................................................... 2
Block Diagram................................................................................................................. 3
Enhanced Sector Protect/Un-protect IPB Program Algorithm ...................................... 15
Lock Register Program Algorithm................................................................................. 16
IPB Program Algorithm ................................................................................................. 18
Maximum Negative Overshoot ..................................................................................... 29
Maximum Positive Overshoot ....................................................................................... 29
Switch Test Circuit ........................................................................................................ 31
Switching Test Waveform ............................................................................................. 31
Instruction Write Operation Waveform.......................................................................... 33
Read Timing Waveform ................................................................................................ 34
#RESET Timing Waveform........................................................................................... 35
Automatic Chip Erase Timing Waveform...................................................................... 36
Automatic Chip Erase Algorithm Flowchart .................................................................. 37
Automatic Sector Erase Timing Waveform................................................................... 38
Automatic Sector Erase Algorithm Flowchart ............................................................... 39
Erase Suspend/Resume Flowchart .............................................................................. 40
Automatic Program Timing Waveform.......................................................................... 41
Accelerated Program Timing Waveform....................................................................... 41
#CE Controlled Write Timing Waveform....................................................................... 42
#WE Controlled Write Timing Waveform ...................................................................... 43
Automatic Programming Algorithm Flowchart .............................................................. 44
Silicon ID Read Timing Waveform................................................................................ 45
Data# Polling Timing Waveform (During Automatic Algorithms) .................................. 46
Status Polling for Word Programming/Erase ................................................................ 47
Status Polling for Write Buffer Program Flowchart ....................................................... 48
Toggling Bit Timing Waveform (During Automatic Algorithms) .................................... 49
Toggle Bit Algorithm...................................................................................................... 50
#BYTE Timing Waveform For Read operations ........................................................... 51
Page Read Timing Waveform....................................................................................... 51
Deep Power Down mode Waveform ............................................................................ 52
Write Buffer Program Flowchart ................................................................................... 52
AC Timing at Device Power-Up .................................................................................... 53
TSOP 48-pin 12x20mm ................................................................................................ 55
TSOP 56-pin 14x20mm ................................................................................................ 56
LFBGA 64-ball 11x13mm ............................................................................................. 57
TFBGA 48-Ball 6x8mm ................................................................................................. 58
Ordering Part Numbering.............................................................................................. 59
Publication Release Date: August 2, 2013
iii Revision H
5 Page 
W29GL064C
7 FUNCTIONAL DESCRIPTION
7.1 Device Bus Operation
Mode Select #Reset
#CE
#WE #OE Address(4)
Data I/O
DQ[7:0]
#BYTE
VIL VIH #WP/ACC
Data I/O DQ[15:8]
Device Reset L
X
XX
X
High-Z
High-Z
High-
Z
L/H
Standby
Mode
VCC±0.3V VCC±0.3V X
X
X
High-Z
High-Z
High-
Z
H
Output
Disable
H
L
HH
X
High-Z
High-Z
High-
Z
L/H
Read Mode
Write
Accelerated
Program
H
H
H
L H L AIN DOUT
DOUT L/H
L
L H AIN
DIN
DQ[14:8]=High-
Z
DIN
Note(1,2)
L L H AIN DIN DQ15=A-1 DIN VHH
Table 7-1
Device Bus Operation
Notes:
1. For High/Low configuration, either the first or last sector was protected if #WP/ACC=VIL.
For Top/Bottom Boot configuration, either the top or bottom two sectors are protected if #WP/ACC=VIL.
2. When #WP/ACC = VIH, the protection conditions of the outmost sector depends on previous protection conditions.
Refer to the enhanced protect feature.
3. DQ[15:0] are input (DIN) or output (DOUT) pins according to the requests of instruction sequence, sector protection,
or data polling algorithm.
4. In Word Mode (#BYTE=VIH), the addresses are A21 to A0. In Byte Mode (#BYTE=VIL), the addresses are A21 to A-1
(DQ15),.
Description
Control Inputs A21
#CE #WE #OE ~12
Read Silicon ID MFR
Code
L
H
L
X
A11 A8 A5 A3
DQ[7:0] DQ[15:8]
~10 A9 ~7 A6 ~4 ~2 A1 A0 T/B H/L BYTE WORD
X VHH X L X L L L 01
X 00
Cycle 1
Cycle 2
Cycle 3
LHL
LHL
LHL
X
X
X
X VHH X L X L L H 7E
X
X VHH X L X H H L 10 0C X
01(T)
X VHH X L X H H H
01 X
00(B)
22
22
22
Sector Lock Status
Verification(1)
L H L SA
X VHH X L X L H L 01/00
X
X
Secure Sector (H) (2) L H L X
X VHH X L X L H H 9A/1A
X
X
Secure Sector (L) (2) L H L X
X VHH X L X L H H 8A/0A
X
X
Table 7-2
Device Bus Operation (continue)
Notes:
1. Sector unprotected code:00h. Sector protected code:01h.
2. Factory locked code: #WP protects high address sector: 9Ah. #WP protects low address sector: 8Ah. Factory
unlocked code: #WP protects high address sector: 1Ah. #WP protects low address sector: 0Ah
Publication Release Date: August 2, 2013
5 Revision H
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet W29GL064C.PDF ] | |
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