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PDF W9864G6JH Data sheet ( Hoja de datos )
| Número de pieza | W9864G6JH | |
| Descripción | 1M X 4 BANKS X 16 BITS SDRAM | |
| Fabricantes | Winbond | |
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W9864G6JH
1M 4 BANKS 16 BITS SDRAM
Table of Contents-
1. GENERAL DESCRIPTION.......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. AVAILABLE PART NUMBER...................................................................................................... 4
4. PIN CONFIGURATION ............................................................................................................... 4
5. PIN DESCRIPTION..................................................................................................................... 5
6. BLOCK DIAGRAM ...................................................................................................................... 6
7. FUNCTIONAL DESCRIPTION.................................................................................................... 7
7.1 Power Up and Initialization.............................................................................................. 7
7.2 Programming Mode Register Set command .................................................................. 7
7.3 Bank Activate Command ................................................................................................ 7
7.4 Read and Write Access Modes ...................................................................................... 7
7.5 Burst Read Command .................................................................................................... 8
7.6 Burst Command .............................................................................................................. 8
7.7 Read Interrupted by a Read............................................................................................ 8
7.8 Read Interrupted by a Write............................................................................................ 8
7.9 Write Interrupted by a Write............................................................................................ 8
7.10 Write Interrupted by a Read............................................................................................ 8
7.11 Burst Stop Command ..................................................................................................... 9
7.12 Addressing Sequence of Sequential Mode..................................................................... 9
7.13 Addressing Sequence of Interleave Mode ...................................................................... 9
7.14 Auto-precharge Command ........................................................................................... 10
7.15 Precharge Command.................................................................................................... 10
7.16 Self Refresh Command ................................................................................................ 10
7.17 Power Down Mode........................................................................................................ 11
7.18 No Operation Command ............................................................................................... 11
7.19 Deselect Command ...................................................................................................... 11
7.20 Clock Suspend Mode.................................................................................................... 11
8. OPERATION MODE ................................................................................................................. 12
9. ELECTRICAL CHARACTERISTICS ......................................................................................... 13
9.1 Absolute Maximum Ratings .......................................................................................... 13
9.2 Recommended DC Operating Conditions .................................................................... 13
9.3 Capacitance .................................................................................................................. 13
Publication Release Date: Oct. 19, 2011
- 1 - Revision A03
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
W9864G6JH
5. PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION
DESCRIPTION
Multiplexed pins for row and column address.
23 ~ 26, 22,
29 ~35
A0A11
Address
Row address: A0A11. Column address: A0A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
20, 21
BS0, BS1
Bank Select
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
2, 4, 5, 7, 8, 10,
11, 13, 42, 44,
45, 47, 48, 50,
DQ0DQ15
51, 53
Data
Input/ Output
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
19 CS Chip Select command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
18
RAS
Row Address
Strobe
the clock RAS , CAS and WE define the
operation to be executed.
17
CAS
Column
Address Strobe Referred to RAS
16
39, 15
38
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
36, 40
WE
UDQM
LDQM
CLK
CKE
VDD
VSS
VDDQ
VSSQ
NC
Write Enable Referred to RAS
Input/output
mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
Clock Inputs
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
Clock Enable When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power
Power for input buffers and logic circuit inside DRAM.
Ground
Ground for input buffers and logic circuit inside
DRAM.
Power for I/O Separated power from VDD, to improve DQ noise
buffer
immunity.
Ground for I/O Separated ground from VSS, to improve DQ noise
buffer
immunity.
No Connection No connection.
-5-
Publication Release Date: Oct. 19, 2011
Revision A03
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
W9864G6JH
7.17 Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be
enabled with CKE held high for a period equal to tCKS (min.) + tCK (min.).
7.18 No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS , CAS , and WE held high at the rising edge of
the clock. A No Operation Command will not terminate a previous operation that is still executing, such
as a burst read or write cycle.
7.19 Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the RAS , CAS , and WE signals become don't Care.
7.20 Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
- 11 -
Publication Release Date: Oct. 19, 2011
Revision A03
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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