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PDF NAU8814 Data sheet ( Hoja de datos )

Número de pieza NAU8814
Descripción Mono Audio Codec
Fabricantes Nuvoton Technology　
Logotipo Nuvoton Technology Logotipo



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NAU8814
1. GENERAL DESCRIPTION
Mono Audio Codec with Speaker Driver and Equalizer
emPowerAudio™
NAU8814 is a cost effective and low power wideband MONO audio CODEC. It is designed for voice telephony
related applications. Functions include 5-band Graphic Equalizer, Automatic Level Control (ALC) with noise gate,
PGA, standard audio interface I2S, PCM with time slot assignment, and on-chip PLL. The device provides one
differential microphone input and one single ended auxiliary input (multi purpose). There are few variable gain
control stages in the audio path. It also includes MONO line output and integrated BTL speaker driver.
The analog inputs have PGA on the front end, allowing dynamic range optimization with a wide range of input
sources. The microphone amplifiers have a programmable gain from -12dB to +35.25dB to handle both amplified
microphones. In addition to a digital high pass filter to remove DC offset voltages, the ADC also features voice
band digital filtering. Voice band data is accepted by the audio interface (I2S). The DAC converter path includes
filtering and mixing, programmable-gain amplifiers (PGA), and soft muting. The digital interfaces, 2-Wire or SPI,
have independent supply voltage to allow integration into multiple supply systems. NAU8814 operates at supply
voltages from 2.5V to 3.6V, although the digital core can operate at voltage as low as 1.71V to save power.
The NAU8814 is specified for operation from -40°C to +85°C, and is available with automotive AEC-Q100
qualification upon request. Please refer to ordering information for AEC-Q100 compliance part number.
2. FEATURES
24-bit signal processing linear Audio CODEC
Audio DAC: 93dB SNR and -84dB THD
Audio ADC: 91dB SNR and -79dB THD
Support variable sample rates from 2.5 - 48kHz
Integrated BTL Speaker Driver 1 W (8Ω / 5V)
Integrated Headset Driver 40mW (16Ω / 3.3V)
Analog I/O
Integrated programmable Microphone Amplifier
Integrated Line Input and Line Output
Earphone / Speaker / Line Output selection
Microphone / Line Inputs selection
Low Noise bias supplied for microphone
On-chip PLL
Interfaces
I2S digital interface PCM time slot assignment
SPI & 2-Wire serial control Interface (I2C style;
/Write capable)
Low Power, Low Voltage
Analog Supply: 2.5V to 3.6V
Digital Supply: 1.71V to 3.6V
Nominal Operating Voltage: 3.3V
Additional features
5-band Graphic Equalizer
Programmable ALC
ADC Notch Filter
Programmable High Pass Filter
Digital A/D-D/A Passthrough
AEC-Q100 & TS16949 compliant device
available upon request
Industrial temperature: range: –40C to +85C
Applications
VoIP Telephones]
Conference speaker-phone
IP PBX
Mobile Telephone Hands-free Kits
Residential & Consumer Intercoms
emPowerAudio™
Datasheet Revision 2.9
Page 1 of 110
June 2016

1 page




NAU8814 pdf
NAU8814
6. Table of Contents
1. GENERAL DESCRIPTION .................................................................................................................................1
2. FEATURES .........................................................................................................................................................1
3. PIN CONFIGURATION .......................................................................................................................................2
4. PIN DESCRIPTION .............................................................................................................................................3
5. BLOCK DIAGRAM..............................................................................................................................................4
6. TABLE OF CONTENTS......................................................................................................................................5
7. LIST OF FIGURES..............................................................................................................................................9
8. LIST OF TABLES .............................................................................................................................................11
9. ABSOLUTE MAXIMUM RATINGS ...................................................................................................................12
10. OPERATING CONDITIONS..............................................................................................................................12
11. ELECTRICAL CHARACTERISTICS.................................................................................................................13
12. FUNCTIONAL DESCRIPTION..........................................................................................................................17
12.1. INPUT PATH..............................................................................................................................................17
12.1.1. The Single Ended Auxiliary Input (AUX) .........................................................................................17
12.1.2. The differential microphone input (MIC- & MIC+ pins)...................................................................19
12.1.2.1. Positive Microphone Input (MIC+) ...........................................................................................20
12.1.2.2. Negative Microphone Input (MIC-)...........................................................................................20
12.1.2.3. PGA Gain Control .....................................................................................................................21
12.1.3. PGA Boost Stage ..............................................................................................................................21
12.2. MICROPHONE BIASING...........................................................................................................................23
12.3. ADC DIGITAL FILTER BLOCK .................................................................................................................25
12.3.1. Programmable High Pass Filter (HPF) ............................................................................................26
12.3.2. Programmable Notch Filter (NF) ......................................................................................................26
12.3.3. Digital ADC Gain Control..................................................................................................................27
12.4. PROGRAMMABLE GAIN AMPLIFIER (PGA)...........................................................................................27
12.4.1. Automatic level control (ALC)..........................................................................................................27
12.4.1.1. Normal Mode .............................................................................................................................30
12.4.1.2. ALC Hold Time (Normal mode Only) ..........................................................................................30
12.4.2. Peak Limiter Mode ............................................................................................................................31
12.4.3. Attack Time........................................................................................................................................32
12.4.4. Decay Times ......................................................................................................................................32
12.4.5. Noise gate (normal mode only)........................................................................................................32
12.4.6. Zero Crossing....................................................................................................................................33
12.5. DAC DIGITAL FILTER BLOCK .................................................................................................................34
12.5.4. Hi-Fi DAC De-Emphasis and Gain Control......................................................................................35
12.5.5. Digital DAC Output Peak Limiter .....................................................................................................36
12.5.6. Volume Boost ....................................................................................................................................36
12.5.7. 5-Band Equalizer ...............................................................................................................................37
12.6. ANALOG OUTPUTS ..................................................................................................................................38
12.6.1. Speaker Mixer Outputs .....................................................................................................................38
12.6.2. MONO Mixer Output ..........................................................................................................................40
12.6.3. Unused Analog I/O ............................................................................................................................41
12.7. GENERAL PURPOSE I/O .........................................................................................................................42
12.7.1. Slow Timer Clock ..............................................................................................................................43
12.7.2. Jack Detect ........................................................................................................................................43
emPowerAudio™
Datasheet Revision 2.9
Page 5 of 110
June 2016

5 Page





NAU8814 arduino
NAU8814
8. List of Tables
Table 1: Pin Description ................................................................................................................................................3
Table 2: Register associated with Input PGA Contro ..................................................................................................19
Table 3: Microphone Non-Inverting Input Impedances.................................................................................................20
Table 4: Microphone Inverting Input Impedances .......................................................................................................20
Table 5: Registers associated with ALC and Input PGA Gain Control ........................................................................21
Table 6: Registers associated with PGA Boost Stage Control ....................................................................................22
Table 7: Register associated with Microphone Bias....................................................................................................23
Table 8: Microphone Bias Voltage Control ..................................................................................................................24
Table 9: Register associated with ADC .......................................................................................................................25
Table 10: High Pass Filter Cut-off Frequencies (HPFAM=1).......................................................................................26
Table 11: Registers associated with Notch Filter Function..........................................................................................26
Table 12: Equations to Calculate Notch Filter Coefficients..........................................................................................27
Table 13: Register associated with ADC Gain ............................................................................................................27
Table 14: Registers associated with ALC Control .......................................................................................................29
Table 15: ALC Maximum and Minimum Gain Values..................................................................................................29
Table 16: Registers associated with DAC Gain Control ..............................................................................................34
Table 17: Registers associated with Equalizer Control ...............................................................................................37
Table 18: Speaker Output Controls.............................................................................................................................40
Table 19: MONO Output Controls ...............................................................................................................................40
Table 20: General Purpose Control.............................................................................................................................43
Table 21: Jack Insert Detect mode..............................................................................................................................43
Table 22: Jack Insert Detect controls ..........................................................................................................................44
Table 23: Thermal Shutdown ......................................................................................................................................44
Table 24: Registers associated with PLL ....................................................................................................................46
Table 25: Registers associated with PLL ....................................................................................................................47
Table 26: PLL Frequency Examples ...........................................................................................................................48
Table 27: Control Interface Selection ..........................................................................................................................49
Table 28: Standard Interface modes ...........................................................................................................................54
Table 29: Audio Interface Control Registers................................................................................................................54
Table 30: Companding Control ...................................................................................................................................60
Table 31: Power up sequence.....................................................................................................................................63
Table 32: Power down Sequence ...............................................................................................................................63
Table 33: Registers associated with Power Saving.....................................................................................................64
Table 34: VDDA 3.3V Supply Current .........................................................................................................................64
Table 35: SPI Timing Parameters ...............................................................................................................................95
Table 36: 2-WireTiming Parameters ...........................................................................................................................96
Table 37: Audio Interface Timing Parameters ...........................................................................................................100
Table 38: MCLK Timing Parameter ...........................................................................................................................100
emPowerAudio™
Datasheet Revision 2.9
Page 11 of 110
June 2016

11 Page







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