|
|
PDF NPCA110B Data sheet ( Hoja de datos )
| Número de pieza | NPCA110B | |
| Descripción | Audio Enhancing Engine and CODEC | |
| Fabricantes | Nuvoton Technology | |
| Logotipo |  |
|
1. NPCA110B  Hay una vista previa y un enlace de descarga de NPCA110B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Nuvoton Confidential
NPCA110B Audio Enhancing Engine and CODEC
February 2012
Revision 1.1
General Description
The Nuvoton NPCA110B device is a member of Nuvoton’s
Sound Enhancing family optimized for low cost TV, portable
devices such as docking stations for MP3-players and mobile
phones, Multi-Media speakers, PC monitor speakers and
Boom boxes.
The NPCA110B integrates Waves MaxxAudio-3 Lite
sound enhancement algorithms. These are proprietary,
patented, psychoacoustic algorithms that compensate for
the acoustic limitations of small CE devices.
MaxxAudio-3 Lite algorithms enable reproduction of rich
content, with a wide dynamic range and a full frequency
range, on a limited audio system. For low-frequency
reproduction, MaxxBass uses a patented psychoacoustic
technique to create a perceived low bass, which can be
extended up to 1.5 octaves lower than the original. This
technique reproduces full and rich sounding bass tones.
Power handling is done by MaxxVolume, which utilizes the
power amplifiers and speakers to their full extent yet avoids
clipping and distortion.
The MaxxAudio-3 Lite software suite provides an additional
algorithm to design a resonance-free audio system: Maxx-
EQ provides a flexible equalizer with 10 bands.
The NPCA110B enables digital control over the volume and
bass, replacing traditional analog potentiometers.
The Maxx family of devices includes:
■ High-performance, 24-bit audio enhancing engine pre-
programmed with Waves MaxxAudio-3 Lite algorithms
■ Optional Audio ADC
■ Optional Audio DAC
■ Digital I/O and other features for high-performance
audio systems
The MaxxAudio Graphical User Interface (GUI) enables
sound engineers to easily tune the device and customize
presettings for different audio products.
Outstanding Features
■ Improves audio quality for low-performance speakers
■ System-level BOM savings
■ Stereo operation
■ I2C controlled
■ 24-bit accuracy
■ Audio algorithms
— MAXXBASS®
— MAXXEQ
— MAXXVOLUME®
■ Audio input
— One I2S or Synchronous Serial Interface (SSI) input
— Up to two stereo analog inputs: typical SNR of
90 dB; typical THD of 75 dB
■ Audio output
— One I2S or SSI output
— Two analog outputs: typical SNR of 96 dB; typical
THD of 86 dB
■ Several General-Purpose digital signals available to
the application (GPIOs)
■ Typical operational power target of less than 0.15W
■ Power-down target of less than 0.5 mW
■ 3.3V operation
System Block Diagram
MP3 Player
FM Radio
Analog Audio
Analog Audio
Controller
I2C (Optional)
SPDIF Rx
or
TV Chipset
I2S
© 2012 Nuvoton Technology Corporation
NPCA110B
I2S
Analog
GPIOs
Power
Amplifiers
Speakers
R
L
AMP
Analog Audio
Headphones
www.nuvoton.com
1 page  
Nuvoton Confidential
Table of Contents
General Description ............................................................................................................................................ 1
Features.............................................................................................................................................................. 2
Revision Record ................................................................................................................................................ 4
1.0 Signal/Pin Description
1.1 CONNECTION DIAGRAM ............................................................................................................. 7
1.2 PIN TYPES ..................................................................................................................................... 8
1.3 PIN DESCRIPTION ........................................................................................................................ 8
1.3.1 Clocks and Reset .............................................................................................................. 8
1.3.2 GPIO ................................................................................................................................ 8
1.3.3 I2S / GPIO / STRAPS ....................................................................................................... 9
1.3.4 I2C / GPIO ........................................................................................................................ 9
1.3.5 CODEC ........................................................................................................................... 10
1.3.6 Power .............................................................................................................................. 10
2.0 Power, Clocks and Reset
2.1 POWER ........................................................................................................................................ 11
2.1.1 Power Planes .................................................................................................................. 11
2.1.2 Power States ................................................................................................................... 11
Illegal Power States ......................................................................................................... 11
2.1.3 Power Connection and Layout Guidelines ...................................................................... 11
Ground Connection ......................................................................................................... 11
Power Connection ........................................................................................................... 12
2.2 CLOCKS ....................................................................................................................................... 15
2.3 RESET SOURCES AND TYPES ................................................................................................. 16
2.3.1 Power-Up Reset .............................................................................................................. 16
2.3.2 Watchdog Reset .............................................................................................................. 16
3.0 Device Specifications
3.1 GENERAL DC ELECTRICAL CHARACTERISTICS .................................................................... 17
3.1.1 Recommended Operating Conditions ............................................................................. 17
3.1.2 Absolute Maximum Ratings ............................................................................................. 17
3.1.3 Capacitance ................................................................................................................... 17
3.1.4 Power Supply Current Consumption under Recommended Operating Conditions ......... 18
3.2 DC CHARACTERISTICS OF PINS BY I/O BUFFER TYPES ...................................................... 18
3.2.1 Input, TTL Compatible ..................................................................................................... 18
3.2.2 Input, TTL Compatible, with Schmitt Trigger ................................................................... 18
3.2.3 Output, TTL/CMOS-Compatible, Push-Pull Buffer .......................................................... 19
3.2.4 Output, TTL/CMOS-Compatible, Open-Drain Buffer ....................................................... 19
3.2.5 Notes and Exceptions ..................................................................................................... 19
3.2.6 Terminology ..................................................................................................................... 19
3.3 INTERNAL RESISTORS .............................................................................................................. 20
3.3.1 Pull-Up Resistors ............................................................................................................. 20
Revision 1.1
5 www.nuvoton.com
5 Page 
Nuvoton Confidential
2.0 Power, Clocks and Reset
2.1 POWER
2.1.1 Power Planes
The NPCA110B has three power plane groups (wells), as shown in Table 2.
Table 2. NPCA110B Power Planes
Power Plane
Group
Description
Power Plane
Notation
Power Pins
Ground Pins
Internal group Powers the internal PLL. Supply is generated internally, but
requires filtering.
Powers the internal logic of all the device modules. Supply
is generated internally but requires filtering.
Active group 3.3V power to the I/O interface and internal regulators.
Analog Active Powers the CODEC; requires filtering
VD18
VD18
VDD
AVDD
VPLL18
VD18
VDD
AVDD
VSSP
VSS
VSS
AGND
For correct NPCA110B operation, AVDD must be applied at the same time that VDD is applied. Protection is provided only
against rise-time differences between the different power planes.
2.1.2 Power States
The NPCA110B has the following main power states:
• Power Fail
All power planes are powered off; (i.e., VDD, AVDD are inactive).
• Power Active
All power planes are powered on (i.e., VDD, AVDD are active).
Illegal Power States
The following power states are illegal (i.e., NPCA110B operation is not guaranteed):
• Active power plane on and analog power plane off.
• Active power plane off and analog power plane on.
2.1.3 Power Connection and Layout Guidelines
The NPCA110B requires a power supply voltage of 3.13V3.47V for the digital supplies (VDD) and 3.00V3.47V for the an-
alog power supply (AVDD).
VDD uses a common ground return named Digital Ground and marked VSS. The analog circuits use a separate ground re-
turn. This ensures effective isolation of the analog modules from noise caused by the digital modules.
The following directives are recommended for the NPCA110B power and ground connections.
Ground Connection
Use two ground planes, one for digital signals (VSS) and one or more for analog signals (AVSS). Make the following ground
connections:
• Connect a specific analog ground plane (AVSS) to the digital ground plane (VSS) at one point only. This point should
be physically located near the relevant NPCA110B analog supply pin, AVDD.
• Connect the analog ground return pin (AGND) of the NPCA110B to the analog ground plane.
• Connect the decoupling capacitors of the analog supply (AVDD) to the analog ground plane, as close as possible to
the AGND pin.
• Connect all VSS pins and the bottom pad of the NPCA110B to the GND plane.
• Locate the decoupling capacitors of the Active power plane’s digital supply (VDD) pins close to a VDD pin; connect
one terminal of each capacitor to the ground plane.
• If there is insufficient room for decoupling capacitors, place smaller capacitors close to the power-ground pins and
larger capacitors further away.
Note that low-impedance ground layers improve noise isolation and reduce ground bounce problems.
Revision 1.1
11 www.nuvoton.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NPCA110B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| NPCA110B | Audio Enhancing Engine and CODEC | Nuvoton Technology |
| NPCA110D | Audio Enhancing Engine | Nuvoton Technology |
| NPCA110M | Audio Enhancing Engine and CODEC | Nuvoton Technology |
| NPCA110P | Audio Enhancing Engine and CODEC | Nuvoton Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |