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PDF NPCA110P Data sheet ( Hoja de datos )
| Número de pieza | NPCA110P | |
| Descripción | Audio Enhancing Engine and CODEC | |
| Fabricantes | Nuvoton Technology | |
| Logotipo |  |
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Nuvoton Confidential
NPCA110P Audio Enhancing Engine and CODEC
February 2012
Revision 1.1
General Description
The Nuvoton NPCA110P device is a member of Nuvoton’s
Sound Enhancing family optimized for portable devices such
as docking stations for MP3-players and mobile phones, Multi-
Media speakers, PC monitor speakers and Boom boxes.
The NPCA110P integrates Waves MaxxAudio 3 sound
enhancement algorithms. These are proprietary, patented,
psychoacoustic algorithms that compensate for the
acoustic limitations of small CE devices.
The MaxxAudio 3 algorithms enable reproduction of rich
content, with a wide dynamic range and a full frequency
range, on a limited audio system. For low-frequency
reproduction, MaxxBass uses a patented psychoacoustic
technique to create a perceived low bass, which can be
extended up to 1.5 octaves lower than the original. This
technique reproduces full and rich sounding bass tones.
Power handling is done by MaxxVolume, which utilizes the
power amplifiers and speakers to their full extent yet avoids
clipping and distortions.
The MaxxAudio 3 software suite provides additional algo-
rithms that enhance the overall sound quality, such as
Maxx3D, which widens the stereo image, and MaxxTreble,
for reproducing crystal clear high frequencies. To design a
resonance-free audio system, MaxxEQ provides a flexible
equalizer with 10 bands.
The NPCA110P enables digital control over the Volume and
Bass, replacing traditional analog potentiometers. Addition-
al digital controls for selecting a specific music style (Jazz,
Vocal, Rap, Classical, etc.) can also be added.
The Maxx family of devices includes:
■ High-performance, 24-bit audio enhancing engine pre-
programmed with Waves MaxxAudio 3 algorithms
■ Optional Audio ADC
■ Optional Audio DAC
■ Digital I/O and other features for high-performance
audio systems
The MaxxAudio Graphical User Interface (GUI) enables
sound engineers to easily tune the device and customize
presettings for different audio products.
Outstanding Features
■ Improves audio quality for low-performance speakers
■ System-level BOM savings
■ Stereo operation
■ I2C controlled
■ 24-bit accuracy
■ Audio algorithms
— MAXXBASS®
—
— MAXXTREBLE
— MAXXEQ
— MAXXVOLUME®
— MAXXLEVELER
— MAXXDIALOG
■ Audio input
— Up to three I2S or Synchronous Serial Interface
(SSI) inputs
— Up to three stereo analog inputs: typical SNR of
90 dB; typical THD of 75 dB
■ Audio output
— Optional generation of bass channel for sub-woofer
— Up to three I2S or SSI outputs
— Up to four analog outputs: typical SNR of 96 dB;
typical THD of 86 dB
■ Several General-Purpose digital signals available to
the application (GPIOs)
■ Typical operational power target of less than 0.2W
■ Power-down target of less than 1 mW
■ 3.3V operation
System Block Diagram
MP3 Player
FM Radio
Controller
SPDIF Rx
CD
Analog Audio
Analog Audio
I2C (Optional)
I2S
I2S
NPCA110P
I2S
Analog
GPIOs
Power
Amplifiers
AMP
Speakers
R
L
Optional
Bass
Analog Audio
Headphones
© 2012 Nuvoton Technology Corporation
www.nuvoton.com
1 page  
Nuvoton Confidential
Table of Contents
General Description ............................................................................................................................................ 1
Features.............................................................................................................................................................. 2
Revision Record ................................................................................................................................................ 4
1.0 Signal/Pin Description
1.1 CONNECTION DIAGRAM ............................................................................................................. 7
1.2 PIN TYPES ..................................................................................................................................... 8
1.3 PIN DESCRIPTION ........................................................................................................................ 8
1.3.1 Clocks and Reset .............................................................................................................. 8
1.3.2 GPIO ................................................................................................................................ 8
1.3.3 I2S / GPIO / STRAPS ....................................................................................................... 9
1.3.4 I2C / GPIO ...................................................................................................................... 10
1.3.5 CODEC ........................................................................................................................... 10
1.3.6 Power .............................................................................................................................. 11
1.3.7 Not Connected ............................................................................................................... 11
2.0 Power, Clocks and Reset
2.1 POWER ........................................................................................................................................ 12
2.1.1 Power Planes .................................................................................................................. 12
2.1.2 Power States ................................................................................................................... 12
Illegal Power States ......................................................................................................... 12
2.1.3 Power Connection and Layout Guidelines ...................................................................... 12
Ground Connection ......................................................................................................... 12
Power Connection ........................................................................................................... 13
2.2 CLOCKS ....................................................................................................................................... 16
2.3 RESET SOURCES AND TYPES ................................................................................................. 17
2.3.1 Power-Up Reset .............................................................................................................. 17
2.3.2 Watchdog Reset .............................................................................................................. 17
3.0 Device Specifications
3.1 GENERAL DC ELECTRICAL CHARACTERISTICS .................................................................... 18
3.1.1 Recommended Operating Conditions ............................................................................. 18
3.1.2 Absolute Maximum Ratings ............................................................................................. 18
3.1.3 Capacitance ................................................................................................................... 18
3.1.4 Power Supply Current Consumption under Recommended Operating Conditions ......... 19
3.2 DC CHARACTERISTICS OF PINS BY I/O BUFFER TYPES ...................................................... 19
3.2.1 Input, TTL Compatible ..................................................................................................... 19
3.2.2 Input, TTL Compatible, with Schmitt Trigger ................................................................... 19
3.2.3 Output, TTL/CMOS-Compatible, Push-Pull Buffer .......................................................... 20
3.2.4 Output, TTL/CMOS-Compatible, Open-Drain Buffer ....................................................... 20
3.2.5 Notes and Exceptions ..................................................................................................... 20
3.2.6 Terminology ..................................................................................................................... 20
3.3 INTERNAL RESISTORS .............................................................................................................. 21
3.3.1 Pull-Up Resistors ............................................................................................................. 21
Revision 1.1
5 www.nuvoton.com
5 Page 
Nuvoton Confidential
1.0 Signal/Pin Description (Continued)
1.3.6 Power
Note: Power connections are found in Figure 1 on page 13 and Figure 2 on page 14.
Signal
VSSP
VPLL18
VD18
VSS
VDD
I/O Description
G PLL Ground. Should be connected to a digital ground plane via a 0 resistor.
P PLL 1.8V Supply. Internally generated for PLL. Should be connected via a 4.7 F ceramic
capacitor to VSSP.
P Internal 1.8V Supply. Internally generated for internal logic. Should be connected via a 4.7 F
ceramic capacitor to digital ground.
G Digital Ground. Should be connected to a digital ground plane. The QFN40 package bottom pad
must be connected to digital ground.
P 3.3V Digital Supply.
1.3.7 Not Connected
Signal
NC
I/O Description
Not Connected. Should be left open and not be connected to any signal.
Revision 1.1
11 www.nuvoton.com
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