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PDF ADF4150 Data sheet ( Hoja de datos )
| Número de pieza | ADF4150 | |
| Descripción | Fractional-N/Integer-N PLL Synthesizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
Fractional-N/Integer-N PLL Synthesizer
ADF4150
FEATURES
GENERAL DESCRIPTION
Fractional-N synthesizer and integer-N synthesizer
Programmable divide-by-1/-2/-4/-8/-16 output
5.0 GHz RF bandwidth
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
Programmable dual-modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
Switched bandwidth fast-lock mode
Cycle slip reduction
APPLICATIONS
The ADF4150 allows implementation of fractional-N or
integer-N phase-locked loop (PLL) frequency synthesizers
if used with an external voltage-controlled oscillator (VCO),
loop filter, and external reference frequency.
The ADF4150 is for use with external VCO parts and is
software compatible with the ADF4350. The VCO frequency
can be divided by 1/2/4/8/16 to allow the user to generate RF
output frequencies as low as 31.25 MHz. For applications that
require isolation the RF output stage can be muted. The mute
function is both pin and software controllable.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.
The ADF4150 is available in a 4 mm × 4 mm package.
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMax, GSM,
PCS, DCS, DECT)
Test equipment
Wireless LANs, CATV equipment
Clock generation
FUNCTIONAL BLOCK DIAGRAM
SDVDD
AVDD
DVDD
VP
RSET
REFIN
CLK
DATA
LE
×2
DOUBLER
10-BIT R
COUNTER
÷2
DIVIDER
DATA REGISTER
FUNCTION
LATCH
INTEGER FRACTION MODULUS
REG
REG
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
LOCK
DETECT
MULTIPLEXER
CHARGE
PUMP
PHASE
COMPARATOR
FLO SWITCH
MUXOUT
SW
LD
CPOUT
DIVIDE-BY-1/
-2/-4/-8/-16
MULTIPLEXER
OUTPUT
STAGE
RF
INPUT
RFOUT+
RFOUT–
PDBRF
RFIN+
RFIN–
ADF4150
CE AGND
Figure 1.
CPGND
SDGND
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADF4150
Data Sheet
Parameter
RF OUTPUT CHARACTERISTICS
Minimum Output Frequency Using RF
Output Dividers
Maximum RFIN Frequency Using RF
Output Dividers
Harmonic Content (Second)
Harmonic Content (Third)
Harmonic Content (Second)
Harmonic Content (Third)
Output Power 3
Min
31.25
Output Power Variation
Level of Signal With RF Mute Enabled
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(PNSYNTH)4
Normalized 1/f Noise (PN1_f)5
Normalized Phase Noise Floor
(PNSYNTH)4
Normalized 1/f Noise (PN1_f)5
B Version
Typ
−19
−13
−20
−10
−4
+5
±1
−40
−223
−123
−222
−119
Max Unit
MHz
4400 MHz
dBc
dBc
dBc
dBc
dBm
dBm
dB
dBm
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Conditions/Comments
500 MHz VCO input and divide-by-16 selected
Fundamental VCO output
Fundamental VCO output
Divided VCO output
Divided VCO output
Maximum setting
Minimum setting
PLL loop BW = 500 kHz (ABP = 3 ns)
10 kHz offset. Normalized to 1 GHz. (ABP = 3 ns)
PLL loop BW = 500 kHz (ABP = 6 ns); low noise
mode selected
10 kHz offset; normalized to 1 GHz; (ABP = 6 ns);
low noise mode selected
Spurious Signals Due to PFD
Frequency6
−90 dBc VCO output
−75 dBc RF output buffers
1 AC coupling ensures AVDD/2 bias.
2 TA = 25°C; AVDD = DVDD = 3.3 V; prescaler = 8/9; fREFIN = 100 MHz; fPFD = 26 MHz; fRF = 1.7422 GHz.
3 Using a tuned load.
4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log FPFD. PNSYNTH = PNTOT − 10logFPFD − 20logN.
5 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (FRF)
and at a frequency offset (f) is given by PN = P1_f + 10log(10 kHz/f) + 20log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
6 Spurious measured on EVAL-ADF4150EB1Z, using a Rohde & Schwarz FSUP signal source analyzer.
Rev. A | Page 4 of 28
5 Page 
ADF4150
–60
–80
–100
–120
–140
–160
–180
1k
10k 100k 1M 10M
FREQUENCY (Hz)
Figure 10. RF Output Phase Noise RF Dividers Used; Integer-N; Low Noise
Mode; VCOOUT = 1750 MHz, REFIN = 100 MHz, PFD = 25 MHz, Loop Filter
Bandwidth = 50 kHz
–60
–80
–100
–120
–140
–160
–180
1k
10k 100k 1M 10M
FREQUENCY (Hz)
Figure 11. RF Buffer Output Fractional-N Phase Noise and Spur Performance;
Low Noise Mode; VCOOUT = 1750 MHz, REFIN = 100 MHz, PFD = 25 MHz,
Loop Filter Bandwidth = 15 kHz, Channel Spacing = 200 kHz; FRAC = 1,
MOD = 5; Output Divider = 1
Data Sheet
–60
–80
–100
–120
–140
–160
–180
1k
10k 100k 1M 10M
FREQUENCY (Hz)
Figure 12. RF Buffer Output Fractional-N Phase Noise and Spur Performance;
Low Noise Mode; VCOOUT = 1750 MHz, REFIN = 100 MHz, PFD = 25 MHz,
Loop Filter Bandwidth = 15 kHz, Channel Spacing = 200 kHz; FRAC = 1,
MOD = 5; Output Divider = 2
–60
–80
–100
–120
–140
–160
–180
1k
10k 100k 1M 10M
FREQUENCY (Hz)
Figure 13. RF Buffer Output Fractional-N Phase Noise and Spur Performance;
Low Noise Mode; VCOOUT = 1750 MHz, REFIN = 100 MHz, PFD = 25 MHz,
Loop Filter Bandwidth = 15 kHz, Channel Spacing = 200 kHz. FRAC = 1,
MOD = 5. Output divider = 4
Rev. A | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
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