PDF NM10 Data sheet ( Hoja de datos )

Número de pieza	NM10
Descripción	Express Chipset
Fabricantes	Intel
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Intel® NM10 Family Express Chipset Datasheet December 2009 www.DataSheet.co.kr Document Number: 322896-001 Datasheet pdf - http://www.DataSheet4U.net/ 1 page 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 Real Time Clock (D31:F0)................................................................................. 129 5.12.1 Update Cycles ...................................................................................... 129 5.12.2 Interrupts ........................................................................................... 130 5.12.3 Lockable RAM Ranges ........................................................................... 130 5.12.4 Century Rollover .................................................................................. 130 5.12.5 Clearing Battery-Backed RTC RAM .......................................................... 131 Processor Interface (D31:F0) ............................................................................ 132 5.13.1 Processor Interface Signals .................................................................... 133 5.13.2 Dual-Processor Issues (Nettop Only) ....................................................... 135 Power Management (D31:F0)............................................................................ 136 5.14.1 Features ............................................................................................. 136 5.14.2 Chipset and System Power States........................................................... 137 5.14.3 System Power Planes ............................................................................ 139 5.14.4 SMI#/SCI Generation ........................................................................... 140 5.14.5 Dynamic Processor Clock Control ............................................................ 142 5.14.6 Dynamic PCI Clock Control (Netbook Only) .............................................. 145 5.14.7 Sleep States ........................................................................................ 147 5.14.8 Thermal Management ........................................................................... 150 5.14.9 Event Input Signals and Their Usage ....................................................... 152 5.14.10ALT Access Mode .................................................................................. 155 5.14.11System Power Supplies, Planes, and Signals ............................................ 158 5.14.12Clock Generators.................................................................................. 161 5.14.13Legacy Power Management Theory of Operation ....................................... 162 System Management (D31:F0).......................................................................... 163 5.15.1 Theory of Operation.............................................................................. 163 5.15.2 Heartbeat and Event Reporting via SMBus ............................................... 164 SATA Host Controller (D31:F2).......................................................................... 168 www.DataSheet.co.kr 5.16.1 Theory of Operation.............................................................................. 170 5.16.2 SATA Swap Bay Support........................................................................ 171 5.16.3 Power Management Operation................................................................ 171 5.16.4 SATA LED............................................................................................ 173 5.16.5 AHCI Operation .................................................................................... 173 High Precision Event Timers .............................................................................. 174 5.17.1 Timer Accuracy .................................................................................... 174 5.17.2 Interrupt Mapping ................................................................................ 175 5.17.3 Periodic vs. Non-Periodic Modes ............................................................. 175 5.17.4 Enabling the Timers .............................................................................. 176 5.17.5 Interrupt Levels ................................................................................... 176 5.17.6 Handling Interrupts .............................................................................. 176 5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors .............................. 177 USB UHCI Host Controllers (D29:F0, F1, F2, and F3)............................................ 177 5.18.1 Data Structures in Main Memory............................................................. 177 5.18.2 Data Transfers to/from Main Memory ...................................................... 178 5.18.3 Data Encoding and Bit Stuffing ............................................................... 178 5.18.4 Bus Protocol ........................................................................................ 178 5.18.5 Packet Formats .................................................................................... 179 5.18.6 USB Interrupts..................................................................................... 179 5.18.7 USB Power Management ....................................................................... 182 5.18.8 USB Legacy Keyboard Operation............................................................. 182 USB EHCI Host Controller (D29:F7) ................................................................... 185 5.19.1 EHC Initialization.................................................................................. 185 5.19.2 Data Structures in Main Memory............................................................. 186 5.19.3 USB 2.0 Enhanced Host Controller DMA ................................................... 186 Datasheet 5 Datasheet pdf - http://www.DataSheet4U.net/ 5 Page 12.1.22BPS—Bridge Proprietary Status Register (PCI-PCI—D30:F0) ............................................................................... 355 12.1.23BPC—Bridge Policy Configuration Register (PCI-PCI—D30:F0) ............................................................................... 356 12.1.24SVCAP—Subsystem Vendor Capability Register (PCI-PCI—D30:F0) ............................................................................... 357 12.1.25SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0)......................... 357 13 LPC Interface Bridge Registers (D31:F0) ............................................................... 358 13.1 PCI Configuration Registers (LPC I/F—D31:F0) .................................................... 358 13.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0) .............................. 359 13.1.2 DID—Device Identification Register (LPC I/F—D31:F0) .............................. 359 13.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0) ................................ 360 13.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0) ....................................... 360 13.1.5 RID—Revision Identification Register (LPC I/F—D31:F0) ............................ 361 13.1.6 PI—Programming Interface Register (LPC I/F—D31:F0) ............................. 361 13.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0) ..................................... 361 13.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0).................................... 362 13.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0) ............................ 362 13.1.10HEADTYP—Header Type Register (LPC I/F—D31:F0).................................. 362 13.1.11SS—Sub System Identifiers Register (LPC I/F—D31:F0)............................. 362 13.1.12CAPP—Capability List Pointer (LPC I/F—D31:F0) ....................................... 363 13.1.13PMBASE—ACPI Base Address Register (LPC I/F—D31:F0) .......................... 363 13.1.14ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0) ............................. 363 13.1.15GPIOBASE—GPIO Base Address Register (LPC I/F — D31:F0) ..................... 364 13.1.16GC—GPIO Control Register (LPC I/F — D31:F0) ........................................ 364 13.1.17PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register (LPC I/F—D31:F0) ........................www..DataS.heet.co..kr ..................................................... 365 13.1.18SIRQ_CNTL—Serial IRQ Control Register (LPC I/F—D31:F0) ................................................................................ 365 13.1.19PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register (LPC I/F—D31:F0) ................................................................................ 366 13.1.20LPC_I/O_DEC—I/O Decode Ranges Register (LPC I/F—D31:F0) ................................................................................ 367 13.1.21LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)................................ 368 13.1.22GEN1_DEC—LPC I/F Generic Decode Range 1 Register (LPC I/F—D31:F0) ................................................................................ 369 13.1.23GEN2_DEC—LPC I/F Generic Decode Range 2Register (LPC I/F—D31:F0) ................................................................................ 369 13.1.24GEN3_DEC—LPC I/F Generic Decode Range 3Register (LPC I/F—D31:F0) ................................................................................ 370 13.1.25GEN4_DEC—LPC I/F Generic Decode Range 4Register (LPC I/F—D31:F0) ................................................................................ 370 13.1.26FWH_SEL1—Firmware Hub Select 1 Register (LPC I/F—D31:F0) ................................................................................ 371 13.1.27FWH_SEL2—Firmware Hub Select 2 Register (LPC I/F—D31:F0) ................................................................................ 372 13.1.28FWH_DEC_EN1—Firmware Hub Decode Enable Register (LPC I/F—D31:F0) ................................................................................ 372 13.1.29BIOS_CNTL—BIOS Control Register (LPC I/F—D31:F0) ................................................................................ 374 13.1.30FDCAP—Feature Detection Capability ID (LPC I/F—D31:F0) ................................................................................ 375 13.1.31FDLEN—Feature Detection Capability Length (LPC I/F—D31:F0) ................................................................................ 375 Datasheet 11 Datasheet pdf - http://www.DataSheet4U.net/ 11 Page

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