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GS8170DW72AC-350 PDF даташит

Спецификация GS8170DW72AC-350 изготовлена ​​​​«GSI Technology» и имеет функцию, называемую «(GS8170DW36AC / GS8170DW72AC) Double Late Write SigmaRAM».

Детали детали

Номер произв GS8170DW72AC-350
Описание (GS8170DW36AC / GS8170DW72AC) Double Late Write SigmaRAM
Производители GSI Technology
логотип GSI Technology логотип 

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GS8170DW72AC-350 Даташит, Описание, Даташиты
GS8170DW36/72AC-350/333/300/250
209-Bump BGA
Commercial Temp
Industrial Temp
18Mb Σ1x1Dp CMOS I/O
Double Late Write SigmaRAM™
250 MHz–350 MHz
1.8 V VDD
1.8 V I/O
Features
• Double Late Write mode, Pipelined Read mode
• JEDEC-standard SigmaRAMpinout and package
• 1.8 V +150/–100 mV core power supply
• 1.8 V CMOS Interface
• ZQ controlled user-selectable output drive strength
• Dual Cycle Deselect
• Burst Read and Write option
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• Byte write operation (9-bit bytes)
• 2 user-programmable chip enable inputs
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb
devices
• Pb-Free 209-bump BGA package available
SigmaRAM Family Overview
GS8170DW36/72A SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. This family of wide,
very low voltage CMOS I/O SRAMs is designed to operate at
the speeds needed to implement economical high performance
networking systems.
ΣRAMs are offered in a number of configurations including
Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by
these RAMs mainly involve various approaches to write
cueing and data transfer rates. The ΣRAMfamily standard
allows a user to implement the interface protocol best suited to
the task at hand.
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
www.DataSheet.co.kr
Functional Description
Because SigmaRAMs are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
ΣRAMs support pipelined reads utilizing a rising-edge-
triggered output register. They also utilize a Dual Cycle
Deselect (DCD) output deselect protocol.
ΣRAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
Parameter Synopsis
Key Fast Bin Specs
Cycle Time
Access Time
Symbol
tKHKH
tKHQV
- 350
2.86 ns
1.7 ns
Rev: 1.04 4/2005
1/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
Datasheet pdf - http://www.DataSheet4U.net/









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GS8170DW72AC-350 Даташит, Описание, Даташиты
GS8170DW36/72AC-350/333/300/250
SigmaRAM Pinouts
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
• 2002.06
256K x 72 Common I/O—Top View (Package C)
1 2 3 4 5 6 7 8 9 10 11
DQg DQg
A
E2
A ADV A
E3
A DQb DQb
DQg DQg
Bc
Bg NC
W
A Bb Bf DQb DQb
DQg DQg
Bh
Bd
NC
E1
NC
Be
Ba DQb DQb
(144M)
DQg DQg VSS NC NC MCL NC NC VSS DQb DQb
DQg
DQc
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQf
DQb
DQc DQc VSS VSS VSS ZQ VSS VSS VSS DQf DQf
DQc
DQc
VDDQ
VDDQ
VDD
EP2
VDD
VDDQ
VDDQ
DQf
DQf
DQc DQc VSS VSS VSS EP3 VSS VSS VSS DQf DQf
DQc
DQc
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQf
DQf
CQ2 CQ2
CK
NC
VSS MCL VSS
NC
NC CQ1 CQ1
DQh
DQh
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
DQh DQh VSS
VSS
VSS
www.DataSheet.co.kr
MCL
VSS
VSS
VSS DQa DQa
DQh
DQh
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
DQh DQh VSS VSS VSS MCL VSS VSS VSS DQa DQa
DQd
DQh
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQa
DQe
DQd DQd VSS NC NC MCL NC NC VSS DQe DQe
DQd DQd
NC
A NC A NC A
(72M)
(36M)
NC DQe DQe
DQd DQd
A
A
A A1 A
A
A DQe DQe
DQd DQd TMS
TDI
A
A0
A TDO TCK DQe DQe
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
Note:
Users of CMOS I/O SigmaRAMs may wish to connect “NC, VREF” and the “NC, CK” pins to VREF (i.e., VDDQ/2) to
allow alternate use of future HSTL I/O SigmaRAMs.
Rev: 1.04 4/2005
2/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
Datasheet pdf - http://www.DataSheet4U.net/









No Preview Available !

GS8170DW72AC-350 Даташит, Описание, Даташиты
GS8170DW36/72AC-350/333/300/250
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
• 2002.06
512K x 36 Common I/O—Top View (Package C)
1 2 3 4 5 6 7 8 9 10 11
NC NC A E2 A ADV A E3 A DQb DQb
NC NC Bc NC
A
W
A Bb NC DQb DQb
NC NC NC Bd NC E1 NC NC Ba DQb DQb
(144M)
NC NC VSS NC NC MCL NC NC VSS DQb DQb
NC
DQc
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
NC
DQb
DQc DQc VSS VSS VSS ZQ VSS VSS VSS NC NC
DQc
DQc
VDDQ
VDDQ
VDD
EP2
VDD
VDDQ
VDDQ
NC
NC
DQc DQc VSS VSS VSS EP3 VSS VSS VSS NC NC
DQc
DQc
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
NC
NC
CQ2 CQ2
CK
NC
VSS MCL VSS
NC
NC CQ1 CQ1
www.DataSheet.co.kr
NC
NC
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
NC NC VSS VSS VSS MCL VSS VSS VSS DQa DQa
NC
NC
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
NC NC VSS VSS VSS MCL VSS VSS VSS DQa DQa
DQd
NC
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQa
NC
DQd DQd VSS NC NC MCL NC NC VSS NC NC
DQd DQd
NC
A NC A NC A
(72M)
(36M)
NC NC NC
DQd DQd
A
A
A A1 A
A
A NC NC
DQd DQd TMS
TDI
A
A0
A TDO TCK
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
NC
NC
Note:
Users of CMOS I/O SigmaRAMs may wish to connect “NC, VREF” and the “NC, CK” pins to VREF (i.e., VDDQ/2) to
allow alternate use of future HSTL I/O SigmaRAMs.
Rev: 1.04 4/2005
3/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
Datasheet pdf - http://www.DataSheet4U.net/










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GSI Technology

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