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PDF HMCAD1051-80 Data sheet ( Hoja de datos )
| Número de pieza | HMCAD1051-80 | |
| Descripción | Single 13/12-Bit 65/80 MSPS A/D Converter | |
| Fabricantes | Hittite | |
| Logotipo |  |
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v01.0411
Features
• 13-Bit Resolution
• 65/80 MSPS Maximum Sampling Rate
• Ultra-Low Power Dissipation: 50/60 mW
• 72 dB SNR @ 8 MHz FIN
• Internal Reference Circuitry
• 1.8 V Core Supply Voltage
• 1.7 - 3.6 V I/O Supply Voltage
• Parallel CMOS Output
• 6 x 6 mm 40-Pin QFN (LP6HE) Package
0 Typical Applications
• Handheld Communication, PMR, SDR
• Medical Imaging
• Portable Test Equipment
• Digital Oscilloscopes
• Baseband / IF Communication
• Video Digitizing
• CCD Digitizing
Functional Diagram
HMCAD1051-80
Single 13/12-Bit 65/80 MSPS
A/D Converter
General Description
The HMCAD1051-80 is a high performance ultra
low power analog-to-digital converter (ADC). The
ADC employs internal reference circuitry, a CMOS
control interface, CMOS output data and is based
on a proprietary structure. Digital error correction is
employed to ensure no missing codes in the complete
full scale range.
Two idle modes with fast startup times exist. The
entire chip can either be put in Standby Mode or
Power Down mode. The two modes are optimized
to allow the user to select the mode resulting in the
lowest possible energy consumption during idle
mode and startup.
The HMCAD1051-80 has a highly linear THA optim-
ized for frequencies up to Nyquist. The differential
clock interface is optimized for low jitter clock sources
and supports LVDS, LVPECL, sine wave and CMOS
clock inputs.
Pin compatible with HMCAD1041-40, HMCAD1041-80
and HMCAD1051-40.
www.DataSheet.net/
0-1
Figure 1. Functional Block Diagram
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
v01.0411
HMCAD1051-80
Single 13/12-Bit 65/80 MSPS
A/D Converter
0
Digital and Timing Specifications
AVDD= 1.8V, DVDD= 1.8V, DVDDCK= 1.8V, OVDD= 2.5V, Conversion Rate: Max specified, 50% clock duty cycle, -1 dBFS input signal, 5 pF capacitive
load on data outputs, unless otherwise noted
Parameter
Condition
Min
Typ
Max
Unit
Clock Inputs
Duty Cycle
20 80 % high
Compliance
CMOS, LVDS, LVPECL, Sine Wave
Input range
Differential input swing
0.4
Vpp
Input range
Differential input swing, sine wave clock input
1.6
Vpp
Input common mode voltage
Keep voltages within ground and voltage of OVDD
0.3
VOVDD -0.3
V
Input capacitance
Differential
2 pF
Timing
TPD
TSLP
TOVR
TAP
Єrms
Start up time from Power Down Mode to Active Mode
Start up time from Sleep Mode to Active Mode
Out of range recovery time
Aperture Delay
Aperture jitter
1
0.8
< 0.5
900 clock cycles
20 clock cycles
clock cycles
ns
ps
TLAT
TD
TDC
Logic Inputs
Pipeline Delay
Output delay (see timing diagram). 5pF load on output bits
Output delay relative to CK_EXT (see timing diagram)
3
1
12 clock cycles
10 ns
6 ns
VHI
VHI
VLI
VLI
IHI
ILI
CI
Logic Outputs
High Level Input Voltage. VOVDD ≥ 3.0V
High Level Input Voltage. VOVDD = 1.7V – 3.0Vwww.DataSheet.net/
Low Level Input Voltage. VOVDD ≥ 3.0V
Low Level Input Voltage. VOVDD = 1.7V – 3.0V
High Level Input leakage Current
Low Level Input leakage Current
Input Capacitance
2V
0.8 ·VOVDD
0
V
0.8 V
0
0.2 ·VOVDD
V
±10 µA
±10 µA
3 pF
VHO
High Level Output Voltage
VOVDD -0.1
V
VLO Low Level Output Voltage
0.1 V
CL
Max capacitive load. Post-driver supply voltage equal to pre-
driver supply voltageVOVDD = VOCVDD
5 pF
CL Max capacitive load. Post-driver supply voltage above 2.25V (1)
10
pF
(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents
and resulting switching noise at a minimum
0-5
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
v01.0411
HMCAD1051-80
Single 13/12-Bit 65/80 MSPS
A/D Converter
Table 3: Data Format Description for 2Vpp Full Scale Range
Differential Input Voltage (IP - IN)
Output data: D_12 : D_0
(DFRMT = 0, Offset Binary)
1.0 V
1 1111 1111 1111
+0.24mV
1 0000 0000 0000
-0.24mV
0 1111 1111 1111
-1.0V
0 0000 0000 0000
Output Data: D_12 : D_0
(DFRMT = 1, 2’s Complement)
0 1111 1111 1111
0 0000 0000 0000
1 1111 1111 1111
1 0000 0000 0000
The data outputs can be used in three different con-
Reference Voltages
figurations.
The reference voltages are internally generated and
0 • Normal mode:
All 13 bits are used. MSB is D_12 and LSB is D_0. This
mode gives optimum performance
• 12-bit mode:
buffered based on a bandgap voltage reference. No
external decoupling is necessary, and the reference
voltages are not available externally. This simplifies
usage of the ADC since two extremely sensitive pins,
otherwise needed, are removed from the interface.
The LSB is left unconnected such that only 12 bits are
used. MSB is D_12 and LSB is D_1. This mode gives
slightly reduced performance due to increased quan-
tization noise.
If a lower full scale range is required the 13-bit output
word provides sufficient resolution to perform digital
scaling with an equivalent impact on noise compared
to adjusting the reference voltages.
• Reduced full scale range mode:
The full scale range is reduced from 2 Vpp to 1 Vpp
which is equivalent to 6 dB gain in the ADC frontend.
Note that data are only available in 2’s complement
format in this mode. MSB is D_11 and LSB is D_0.
Note that the codes will wrap around when exceeding
the full scale range, and that out of range bits should
be used to clamp output data. See section Reference
Voltages for details. This mode gives slightly reduced
performance
A simple way to obtain 1.0 Vpp input range with a
12-bit output word is shown in table 4. Note that only
2’s complement output data are available in this mode
andwww.DataSheet.net/ that out of range conditions must be determined
based on a two bit output. The output code will wrap
around when the code goes outside the full scale
range. The out of range bits should be used to clamp
the output data for over range conditions.
Table 4: Data Format Description for 1Vpp Full Scale Range
Differential Input Volt-
age (IP - IN)
Output Data D_11:D_0
(DFRMT = 0)
(2’s Complement)
Out of Range
(Use Logical AND Function for &)
Output Data
D_11:D_0
(DFRMT = 1)
(2’s Complement)
> 0.5V
0111 1111 1111
D_12 = 1 & D_11 = 1
0111 1111 1111
0.5V
0111 1111 1111
0111 1111 1111
+0.24mV
0000 0000 0000
0000 0000 0000
-0.24mV
1111 1111 1111
1111 1111 1111
-0.5V
1000 0000 0000
1000 0000 0000
< -0.5V
1000 0000 0000
D_12 = 0 & D_11 = 0
1000 0000 0000
Out of Range
(Use Logical AND Function for &)
D_12 = 0 & D_11 = 1
D_12 = 1 & D_11 = 0
0 - 11
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
| Páginas | Total 14 Páginas | |
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