PDF HMCAD1510 Data sheet ( Hoja de datos )

Número de pieza	HMCAD1510
Descripción	High Speed Multi-Mode 8-Bit 30 to 500 MSPS A/D Converter
Fabricantes	Hittite
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No Preview Available ! v03.0711 Features • 8-bit High Speed Single/ Dual/ Quad ADC Single Channel Mode: FSmax = 500 MSPS Dual Channel Mode: FSmax = 250 MSPS Quad Channel Mode: FSmax = 125 MSPS • Integrated Cross Point Switches (Mux Array) • 1X to 50X Digital Gain. No Missing Codes up to 32X • 1X Gain: 49.8 dB SNR. 10X Gain: 48 dB SNR • Internal Low Jitter Programmable Clock Divider • Ultra Low Power Dissipation 0 295 mW Including I/O at 500 MSPS and Reduced Bias • 0.5 µs Start-up Time From Sleep, 15 µs From Power Down • Internal Reference Circuitry with no External Components Required Functional Diagram HMCAD1510 High Speed Multi-Mode 8-Bit 30 to 500 MSPS A/D Converter • Coarse and Fine Gain Control • Digital Fine Gain Adjustment for each ADC • Internal Offset Correction • 1.8V Supply Voltage • 1.7 - 3.6V CMOS Logic on Control Interface Pins • Serial LVDS/RSDS Output • 7 x 7 mm QFN 48 (LP7D) Package Typical Applications • USB Powered Oscilloscopes • Digital Oscilloscopes • Satellite Receivers Pin compatible parts • HMCAD1510 is pin compatible with HMCAD1511 and HMCAD1520 www.DataSheet.net/ 0-1 Figure 1. Functional Block Diagram For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: [email protected] Datasheet pdf - http://www.DataSheet4U.co.kr/ 1 page v03.0711 HMCAD1510 High Speed Multi-Mode 8-Bit 30 to 500 MSPS A/D Converter 0 Digital and Switching Specifications AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, RSDS output data levels, unless otherwise noted Parameter Description TSU Start up time from Power Down Mode and Deep Sleep Mode to Active Mode in µs. See section “Clock Frequency” for details. TSLPCH Start up time from Sleep Channel Mode to Active Mode TOVR Out of range recovery time TLATHSMQ Pipeline delay, Quad Channel Mode TLATHSMD Pipeline delay, Dual Channel Mode TLATHSMS Pipeline delay, Single Channel Mode LVDS Output Timing Characteristics Min tdata TPROP LCLK to data delay time (excluding programmable phase shift) Clock propagation delay. LVDS bit-clock duty-cycle 6TLVDS +2.2 45 Frame clock cycle-to-cycle jitter TEDGE TCLKEDGE Data rise- and fall time 20% to 80% Clock rise- and fall time 20% to 80% Typ 15 1 32 64 128 50 7TLVDS +3.5 0.7 0.7 Max Unit µs µs clock cycles clock cycles clock cycles clock cycles 7TLVDS +5.0 55 2.5 ps ns % LCLK cycle % LCLK cycle ns ns Table 1: Maximum Voltage Ratings Pin Reference pin Rating AVDD AVSS -0.3V to +2.3V DVDD DVSS -0.3V to +2.3V OVDD AVSS -0.3V to +3.9V AVSS / DVSS DVSS / AVSS -0.3V to +0.3V Analog inputs and outputs AVSS -0.3V to +2.3V CLKx AVSS -0.3V to +3.9V LVDS outputs DVSS -0.3V to +2.3V Digital inputs DVSS -0.3V to +3.9V Applying voltages to the pins beyond those specified in Table 1 could cause permanent damage to the circuit. ELECTROSTATIC SENSITIVE DEVICE OBSERVE HANDLING PRECAUTIONS www.DataSheet.net/ Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2: Maximum Temperature Ratings Operating Temperature -40 to +85 °C Storage Temperature -60 to +150 °C Maximum Junction Temperature 110 °C Thermal Resistance (Rth) 29 °C/W Soldering Profile Qualification J-STD-020 ESD Sensivity HBM Class 1C ESD Sensivity CDM Class III 0-5 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: [email protected] Datasheet pdf - http://www.DataSheet4U.co.kr/ 5 Page 0 v03.0711 HMCAD1510 High Speed Multi-Mode 8-Bit 30 to 500 MSPS A/D Converter Register Map Summary Table 5: Register Map Name Description Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hex Address rst sleep4_ch <4:1> sleep2_ch <2:1> sleep1_ch1 sleep pd pd_pin_cfg <1:0> ilvds_lclk <2:0> ilvds_frame <2:0> ilvds_dat <2:0> en_lvds_ term term_lclk <2:0> term_frame <2:0> term_dat <2:0> invert4_ch <4:1> Self-clearing software reset. Inactive Channel-specific sleep mode for a Quad Channel setup. Inactive Channel-specific sleep mode for a Dual Channel setup. Inactive Channel-specific sleep mode for a Single Channel setup. Inactive Go to sleep-mode. Inactive Go to power-down. Inactive Configures the PD pin function. PD pin configured for power-down mode LVDS current drive programmability for LCLKP and LCLKN pins. 3.5 mA drive LVDS current drive programmability for FCLKP and FCLKN pins. 3.5 mA drive LVDS current drive programmability for output data pins. 3.5 mA drive Enables internal termination for LVDS buffers. Termination disabled Programmable termination for LCLKN and LCLKP buffers. Termination disabled Programmable termination for FCLKN and FCLKP buffers. Termination disabled Programmable termination for output data buffers. Termination disabled Channel specific swapping of the analog input signal for a Quad Channel setup. IPx is positive input X X XX X 1 1 1 www.DataSheet.net/ X XX X XX X X XXX 0x00 XX X 0x0F XXX XXX 0x11 XXX XXX 0x12 X XXX invert2_ch <2:1> invert1_ch1 en_ramp Channel specific swapping of the analog input signal for a Dual Channel setup. Channel specific swapping of the analog input signal for a Single Channel setup. Enables a repeating full-scale ramp pattern on the outputs. IPx is positive input IPx is positive input Inactive XX X X00 0x24 dual_ custom_pat Enable the mode wherein the output toggles between two defined codes. Inactive 0X0 0x25 single_ custom_pat Enables the mode wherein the output is a constant specified code. bits_custom1 <7:0> Bits for the single custom pattern and for the first code of the dual custom pattern. bits_custom2 Bits for the second code of the dual <7:0> custom pattern. cgain4_ch1 <3:0> Programmable coarse gain channel 1 in a Quad Channel setup. cgain4_ch2 <3:0> Programmable coarse gain channel 2 in a Quad Channel setup. cgain4_ch3 <3:0> Programmable coarse gain channel 3 in a Quad Channel setup. cgain4_ch4 <3:0> Programmable coarse gain channel 4 in a Quad Channel setup. Inactive 0x00 0x00 1x gain 1x gain 1x gain 1x gain 00X X X X X X X XX 0x26 X X X X X X XX 0x27 X XXX XXXX X X XX 0x2A XXXX 0 - 11 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: [email protected] Datasheet pdf - http://www.DataSheet4U.co.kr/ 11 Page

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