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PDF W25Q40BL Data sheet ( Hoja de datos )
| Número de pieza | W25Q40BL | |
| Descripción | 2.5V 4M-BIT SERIAL FLASH MEMORY | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W25Q40BL
2.5V 4M-BIT
SERIAL FLASH MEMORY WITH
DUAL AND QUAD SPI
Publication Release Date: May 04, 2012
- 1 - Revision D
1 page  
W25Q40BL
1. GENERAL DESCRIPTION
The W25Q40BL (4M-bit) Serial Flash memory provides a storage solution for systems with limited space,
pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash
devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP)
and storing voice, text and data. The device operates on a single 2.3V to 3.6V power supply with current
consumption as low as 4mA active and 1µA for power-down. All devices are offered in space-saving
packages.
The W25Q40BL array is organized into 2,048 programmable pages of 256-bytes each. Up to 256 bytes
can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128
(32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q40BL has
128 erasable sectors and 8 erasable blocks respectively. The small 4KB sectors allow for greater flexibility
in applications that require data and parameter storage. (See figure 2.)
The W25Q40BL supports the standard Serial Peripheral Interface (SPI), and a high performance
Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1
(DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 80MHz are supported allowing
equivalent clock rates of 160MHz (80MHz x 2) for Dual I/O and 320MHz (80MHz x 4) for Quad I/O when
using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard
Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient
memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP
(execute in place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top, bottom or complement array
control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer
and device identification with a 64-bit Unique Serial Number.
2. FEATURES
• Family of SpiFlash Memories
– W25Q40BL: 4M-bit/512K-byte (524,288)
– 256-byte per programmable page
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
• Highest Performance Serial Flash
– 80MHz Dual/Quad SPI clocks
– 160/320MHz equivalent Dual/Quad SPI
– 40MB/S continuous data transfer rate
– Up to 5X that of ordinary Serial Flash
– More than 100,000 erase/program cycles
– More than 20-year data retention
• Efficient “Continuous Read Mode”
– Low Instruction overhead
– Continuous Read with 8/16/32/64-Byte Wrap
– As few as 8 clocks to address memory
– Allows true XIP (execute in place) operation
– Outperforms X16 Parallel Flash
• Low Power, Wide Temperature Range
– Single 2.3 to 3.6V supply
– 4mA active current, <1µA Power-down current
– -40°C to +85°C operating range
• Flexible Architecture with 4KB sectors
– Uniform Sector Erase (4K-bytes)
– Uniform Block Erase (32K and 64K-bytes)
– Program one to 256 bytes
– Erase/Program Suspend & Resume
• Advanced Security Features
– Software and Hardware Write-Protect
– Top/Bottom, 4KB complement array protection
– Lock-Down and OTP array protection
– 64-Bit Unique Serial Number for each device
– Discoverable Parameters (SFDP) Register
– 3X256-Byte Security Registers with OTP locks
– Volatile & Non-volatile Status Register Bits
• Space Efficient Packaging
– 8-pin SOIC / VSOP / PDIP
– 8-pad WSON 6x5-mm, USON 2x3-mm
– Contact Winbond for KGD and other options
Publication Release Date: May 04, 2012
- 5 - Revision D
5 Page 
W25Q40BL
7. CONTROL AND STATUS REGISTERS
The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the
availability of the Flash memory array, if the device is write enabled or disabled, the state of write
protection, Quad SPI setting, Security Register lock status and Erase/Program Suspend status. The Write
Status Register instruction can be used to configure the device write protection features, Quad SPI setting
and Security Register OTP lock. Write access to the Status Register is controlled by the state of the non-
volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and during Standard/Dual
SPI operations, the /WP pin.
7.1 STATUS REGISTER
7.1.1 BUSY
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a
Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or
Erase/Program Security Register instruction. During this time the device will ignore further instructions
except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and
tCE in AC Characteristics). When the program, erase or write status/security register instruction has
completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.
7.1.2 Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase
Security Register and Program Security Register.
7.1.3 Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and
S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status
Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be
protected from Program and Erase instructions (see Status Register Memory Protection table). The
factory default setting for the Block Protection Bits is 0, none of the array protected.
7.1.4 Top/Bottom Block Protect (TB)
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the
Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.
The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction
depending on the state of the SRP0, SRP1 and WEL bits.
7.1.5 Sector/Block Protect (SEC)
The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect
either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array
as shown in the Status Register Memory Protection table. The default setting is SEC=0.
- 11 -
Publication Release Date: May 04, 2012
Revision D
11 Page | ||
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| PDF Descargar | [ Datasheet W25Q40BL.PDF ] | |
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