PDF HMC1035LP6GE Data sheet ( Hoja de datos )

Número de pieza	HMC1035LP6GE
Descripción	+3.3 V clock generator
Fabricantes	Hittite
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No Preview Available ! HMC1035LP6GE v01.0712 High Performance, +3.3 V Clock Generator 25 - 2500 MHz Typical Applications • 10G/40G/100G Optical Modules, Transponders, Line Cards • OTN and SONET/SDH Applications • Data Converters, Sample Clock Generation • Cellular/4G Infrastructure • High Frequency Processor/FPGA Clocks • Any Frequency Clock Rate Generation • Low Jitter SAW Oscillator Replacement • DDS Replacement • Frequency Translation • Frequency Margining Functional Diagram Features 3.3 V Only, Single Supply Rail Operation Output Frequency Range: 25 MHz - 2500 MHz Integer or Fractional-N mode Frequency Translation Configurable LVDS-compatible or LVPECL type Differential Outputs “Power Priority” and“Performance Priority” modes 97 fs RMS Jitter Generation (12 kHz - 20 MHz, 2500 MHz, Typ) -163 dBc/Hz Phase Noise Floor to Improve ADC/DAC SNR (maximum output swing levels). Adjustable PLL Loop BW via External Filter Output Disable/Mute Control Lock Detect Signal Exact Frequency Mode to achieve reference frequency tuning, and 0 Hz frequency error 40 Lead 6x6 mm SMT Package: 36 mm2 www.DataSheet.net/ For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 1 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or [email protected] Datasheet pdf - http://www.DataSheet4U.co.kr/ 1 page HMC1035LP6GE v01.0712 High Performance, +3.3 V Clock Generator 25 - 2500 MHz Figure 1. Typical Phase Noise, Integer Mode, Power Priority[1] -100 -110 -120 -130 -140 -150 -160 -170 -180 1 625 MHz_LVDS 625 MHz_LVPECL 2500 MHz_LVDS 2500 MHz_LVPECL 10 100 1000 OFFSET(KHz) 10000 100000 Figure 2. Typical Phase Noise, Integer Mode, Performance Priority[1] -100 -110 -120 -130 -140 -150 -160 -170 625 MHz_LVDS 625 MHz_LVPECL 2500 MHz_LVDS 2500 MHz_LVPECL -180 1 10 100 1000 10000 100000 OFFSET(KHz) Figure 3. Typical Phase Noise, Fractional Mode, Power Priority[1] -100 -110 -120 -130 -140 -150 -160 -170 622.08 MHz_LVDS 622.08 MHz_LVPECL 2500 MHz_LVDS 2500 MHz_LVPECL -180 1 10 100 1000 10000 100000 OFFSET(KHz) Figure 4. Typical Phase Noise, Fractional Mode, Performance Priority[1] -100 -110 -120 -130 www.DataSheet.net/ -140 -150 -160 -170 622.08 MHz_LVDS 622.08 MHz_LVPECL 2500 MHz_LVDS 2500 MHz_LVPECL -180 1 10 100 1000 10000 100000 OFFSET(KHz) Figure 5. Integer Phase Noise vs Reference Source[2] -80 Figure 6. Jitter from Integrated Phase Noise vs Output Frequency, Integer Mode[2] 160 -100 -120 140 120 100 -140 -160 -180 1 XO OCXO 10 100 1000 OFFSET(KHz) 10000 100000 80 60 40 LVDS_PWR_PRI LVDS_PERF_PRI LVPECL_PWR_PRI LVPECL_PWR_PRI 625 FREQUENCY (MHz) 2500 [1] The PN plot is measured with a 100MHz OCXO followed with a divide by 2, using the Loop Filter in the Loop Filter Configuration Table [2] The PN plot is measured with 50 MHz Crystal Oscillator (red) versus a 50MHz OCXO (blue). [3] Jitter is Integrated over a 12kHz to 20MHz Band For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 5 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or [email protected] Datasheet pdf - http://www.DataSheet4U.co.kr/ 5 Page HMC1035LP6GE v01.0712 High Performance, +3.3 V Clock Generator 25 - 2500 MHz HMC1035LP6GE Input Stage A representative schematic for the HMC1035LP6GE output stage is given in Figure 17 below. The buffer is internally DC biased with 100 ohm internal termination. For 50 ohm match, an external 100 ohm resistor to ground should be added, followed by an AC coupling capacitor (impedance < 1 ohm) then to the XREFP pin of the part. Figure 17. Input Stage HMC1035LP6GE Output Stage A representative schematic for the HMC1035LP6GE output stage is given in Figure 18 below. The output is derived from an emitter which can be internally biased to a current source (the default setting), or the Internal Termination switch can be opened, VCO_Reg03[4], and external termination used. The internal bias would be used when LVDS levels are required and the load would normally be a 100 differential load as shown in Figure 19. With the internal bias set, the HMC1035LP6GE output can also be used to drive 50 ohmwww.DataSheet.net/ single ended loads, see Figures 19 and 20. This would simplify LVPECL designs and reduce component cost. Figure 18. Output Stage Figure 19. AC Coupling into 100 Ohm Differential Load Figure 20. AC Coupling into a 50 Ohm Load For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 11 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or [email protected] Datasheet pdf - http://www.DataSheet4U.co.kr/ 11 Page

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