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H5TQ2G83BFR-xxI PDF даташит

Спецификация H5TQ2G83BFR-xxI изготовлена ​​​​«Hynix Semiconductor» и имеет функцию, называемую «2Gb DDR3 SDRAM».

Детали детали

Номер произв H5TQ2G83BFR-xxI
Описание 2Gb DDR3 SDRAM
Производители Hynix Semiconductor
логотип Hynix Semiconductor логотип 

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H5TQ2G83BFR-xxI Даташит, Описание, Даташиты
2Gb DDR3 SDRAM
2Gb DDR3 SDRAM
Lead-Free&Halogen-Free
(RoHS Compliant)
H5TQ2G83BFR-xxC
H5TQ2G83BFR-xxI
H5TQ2G63BFR-xxC
http://www.DataSheet4U.net/
H5TQ2G63BFR-xxI
* Hynix Semiconductor reserves the right to change products or specifications without notice.
Rev. 1.7 / Dec. 2010
1
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H5TQ2G83BFR-xxI Даташит, Описание, Даташиты
Revision History
Revision No.
0.1
0.2
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
History
Initial Release
Added IDD Specification
Add supported CL5
Modify the package outline with x16
Low power added
M8 pin ball out update
Added 1866 speed Suppport
Added 2133 speed Suppport
Added IDD Specification(2133 speed)
Modify OPERATING FREQUENCY Table
Draft Date
Dec. 2009
Feb. 2010
Jun. 2010
Jun. 2010
Sep. 2010
Sep. 2010
Nov. 2010
Dec. 2010
Dec. 2010
Dec. 2010
http://www.DataSheet4U.net/
Remark
Rev. 1.7 / Dec. 2010
2
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H5TQ2G83BFR-xxI Даташит, Описание, Даташиты
Description
The H5TQ2G83BFR and H5TQ2G63BFR are a 2,147,483,648-bit CMOS Double Data Rate III (DDR3) Syn-
chronous DRAM, ideally suited for the main memory applications which requires large memory density and
high bandwidth. Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and
falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK
(falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and
falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high band-
width.
Device Features and Ordering Information
FEATURES
• VDD=VDDQ=1.5V +/- 0.075V
• 8banks
• Fully differential clock inputs (CK, CK) operation
• Average Refresh Cycle (Tcase of0 oC~95oC)
• Differential Data Strobe (DQS, DQS)
- 7.8 µs at 0oC ~ 85 oC
• On chip DLL align DQ, DQS and DQS transition with CK - 3.9 µs at 85oC ~ 95 oC
transition
Commercial Temperature (0 oC~ 85 oC)
• DM masks write data-in at the both rising and falling Industrial Temperature ( -40oC~ 85 oC)
edges of the data strobe
• Auto Self Refresh supported
• All addresses and control inputs except data,
data strobes and data masks latched on the
rising edges of the clock
• JEDEC standard 82ball FBGA(x8), 96ball FBGA (x16)
• Driver strength selected by EMRShttp://www.DataSheet4U.net/
• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13 • Dynamic On Die Termination supported
and 14 supported
• Asynchronous RESET pin supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9,
10
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre-fetch
• BL switch on the fly
* This product in compliance with the RoHS directive.
Rev. 1.7 / Dec. 2010
3
datasheet pdf - http://www.DataSheet4U.net/










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