H27UCG8T2MYR Datasheet PDF - Hynix
| Part Number | H27UCG8T2MYR | |
| Description | 64Gb (8192M x 8bit) NAND Flash | |
| Manufacturers | Hynix | |
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There is a preview and H27UCG8T2MYR download ( pdf file ) link at the bottom of this page. Total 63 Pages | ||
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H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
64Gb Flash
H27UCG8T2M
http://www.DataSheet4U.net/
Rev 1.0/ Aug. 2010
1
datasheet pdf - http://www.DataSheet4U.net/
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1.2. PIN DESCRIPTION
H27UCG8T2M Series
64Gb (8192M x 8bit) NAND Flash
Pin Name
Description
I/O0-I/O7
DATA INPUTS/OUTPUTS
The I/O pins is used to COMMAND LATCH cycle, ADDRESS INPUT cycle, and DATA in-out cycles during
read / write operations. The I/O pins float to High-Z when the device is deselected or the outputs are
disabled.
COMMAND LATCH ENABLE
CLE This input activates the latching of the I/O inputs inside the Command Register on the Rising edge of Write
Enable (WE#).
ADDRESS LATCH ENABLE
ALE This input activates the latching of the I/O inputs inside the Address Register on the Rising edge of Write
Enable (WE#).
CHIP ENABLE
This input controls the selection of the device. When the device is busy, CE# low does not deselect the
CE# memory. The device goes into Stand-by mode when CE# goes High during the device is in Ready state.
The CE# signal is ignored when device is in Busy state, and will not enter Standby mode even if the CE#
goes high.
WE#
WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The I/O inputs are latched on the rise edge
of WE#.
READ ENABLE
RE# The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid tREA after the falling edge of RE# which also increments the internal column address counter by one.
WP#
WRITE PROTECT
The WP# pin, when Low, provides a hardware protection against undesired write operations. Hardware
http://www.DataSheet4U.net/
Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to
ensure the protection even during the power up phases.
R/B#
READY / BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
VccQ SUPPLY VOLTAGE FOR I/O BUFFER
VssQ
GROUND FOR I/O BUFFER
Vcc
SUPPLY VOLTAGE
The VCC supplies the power for all the operations. (Read, Write, and Erase).
Vss GROUND
NC NO CONNECTED
Note:
A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the
current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during pro
gram and erase operations.
Rev 1.0 / Aug. 2010
5
datasheet pdf - http://www.DataSheet4U.net/
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for H27UCG8T2MYR electronic component. |
| Information | Total 63 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ H27UCG8T2MYR.PDF Datasheet ] | |
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