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PDF H27UCG8U5BTR-BC Data sheet ( Hoja de datos )
| Número de pieza | H27UCG8U5BTR-BC | |
| Descripción | 32Gb(4096M x 8bit) Legacy MLC NAND Flash | |
| Fabricantes | Hynix | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de H27UCG8U5BTR-BC (archivo pdf) en la parte inferior de esta página. Total 57 Páginas | ||
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Preliminary
H27UBG8T2BTR-BC Series
32Gb(4096M x 8bit) Legacy MLC NAND Flash
F26 32Gb MLC
NAND Flash Memory
TSOP Legacyhttp://www.DataSheet4U.net/
H27UBG8T2BTR-BC
H27UCG8U5BTR-BC
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev 0.7 / Jan. 2011
1
datasheet pdf - http://www.DataSheet4U.net/
1 page  
Preliminary
H27UBG8T2BTR-BC Series
32Gb(4096M x 8bit) Legacy MLC NAND Flash
3.18. Random Data Input Timings………………………………………………………………………………… 33
3.19. Multi Plane Page Program Operation Timings………………………………………………………….. 34
3.20. Copy-Back Program Operation Timings with Random Date Input.………………………………..
3.21. Cache Program Operation Timings…………………………………………………………………………
35
35
3.22. Multi Plane Cache Program Operation Timings…………………………………………………………. 36
3.23. Block Erase Operation Timings……………………………………………………………………………… 36
3.24. Multi Plane Erase Operation Timings...................................................................................... 37
3.25. Reset Timings…………………………………………………………………………………………………… 37
4. DEVICE OPERATION……………………………………………………………………………………………… 38
4.1. Page Read………………………………………………………………………………………………………….. 38
4.2. Cache Read………………………………………………………………………………………………………… 39
4.3. Cache Read Enhanced ………………………………………………………………………………………….. 39
4.4. Multi Plane Page Read………………………………………………………………………………………….. 40
4.5. Multi Plane Cache Read ……………………………………………………………………………………….. 41
4.6. Multi Plane Cache Read Enhanced ………………………………………………………………………….. 41
4.7. Read ID…………………………………………………………………………………………………………….. 42
4.8. Read Status Register……………………………………………………………………………………………. 43
4.9. Page Program…………………………………………………………………………………………………….. 44
4.10. Multi Plane Program…………………………………………………………………………………………… 45
4.11. Cache Program.…………………………………………………………………………………………………. 46
4.12. Multi Plane Cache Program.…………………………………………………………………………………. 48
4.13. Copy-Back Program……………………………………………………………………………………………. 49
4.14. Multi-Plane Copy-Back Program……………………………………………………………………………. 50
4.15. Block Erase……………………………………………………http://www.DataSheet4U.net/ ………………………………………………….. 51
4.16. Multi Plane Block Erase……………………………………………………………………………………….. 52
4.17. Reset………………………………………………………………………………………………………………. 52
5. OTHER FEATURES………………………………………………………………………………………………….. 53
5.1. Data Protection & Power on/off Sequence………………………………………………………………… 53
5.2. Ready / Busy.……………………………………………………………………………………………………… 54
5.3. Write Protect Operation………………………………………………………………………………………… 55
6. Application Notes and Comments……………………………………………………………………………. 56
6.1. Paired Page Address Information.…………………………………………………………………………… 56
6.2. Acceptable Command after 80h……………………………………………………………………………… 57
6.3. Acceptable Command between Start command and Confirm command…………………………... 57
6.4. Restriction of Read Status Value in Multi Plane Operation……………………………………………. 57
6.5. Page Program Failure…………………………………………………………………………………………… 57
6.6. Restriction Multi Plane Operation.…………………………………………………………………………… 57
Rev 0.7 / Jan. 2011
5
datasheet pdf - http://www.DataSheet4U.net/
5 Page 
Preliminary
H27UBG8T2BTR-BC Series
32Gb(4096M x 8bit) Legacy MLC NAND Flash
1.7. Addressing
1.7.1. Addressing(MLC mode)
Bus cycle
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
1st Cycle
A0 A1 A2 A3 A4 A5 A6 A7
2nd Cycle
A8 A9 A10 A11 A12 A13 L(1) L(1)
3rd Cycle
A14 A15 A16 A17 A18 A19 A20 A21
4th Cycle
A22 A23 A24 A25 A26 A27 A28 A29
5th Cycle
A30 A31 A32 L(1) L(1) L(1) L(1) L(1)
Notes:
1. L must be set to Low.
2. The device ignores any additional address input cycle than required.
3. The Address consists of column address (A0~A13), page address (A14 ~ A21), plane address (A22),
and block address (A23 ~ the last address).
1.7.2. Addressing(SLC mode)
Bus cycle
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
I/O0
A0
A8
A14
A22
A30
I/O1
A1
A9
A15
A23
A31
I/O2
A2
A10
A16
A24
L(1)
http://www.DataSheet4U.net/
I/O3
A3
A11
A17
A25
L(1)
I/O4
A4
A12
A18
A26
L(1)
I/O5
A5
A13
A19
A27
L(1)
I/O6
A6
L(1)
A20
A28
L(1)
I/O7
A7
L(1)
A21
A29
L(1)
Notes:
1. L must be set to Low.
2. The device ignores any additional address input cycle than required.
3. The Address consists of column address (A0~A13), page address (A14 ~ A20), plane address (A21),
and block address (A22 ~ the last address).
Rev 0.7 / Jan. 2011
11
datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 57 Páginas | |
| PDF Descargar | [ Datasheet H27UCG8U5BTR-BC.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
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