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H5TQ1G43BFR-xxC PDF даташит

Спецификация H5TQ1G43BFR-xxC изготовлена ​​​​«Hynix Semiconductor» и имеет функцию, называемую «1Gb DDR3 SDRAM».

Детали детали

Номер произв H5TQ1G43BFR-xxC
Описание 1Gb DDR3 SDRAM
Производители Hynix Semiconductor
логотип Hynix Semiconductor логотип 

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H5TQ1G43BFR-xxC Даташит, Описание, Даташиты
1Gb DDR3 SDRAM
1Gb DDR3 SDRAM
Lead-Free&Halogen-Free
(RoHS Compliant)
H5TQ1G43BFR-xxC
H5TQ1G83BFR-xxC
H5TQ1G63BFR-xxC
http://www.DataSheet4U.com/
*Hynix Semiconductor reserves the right to change products or specifications without notice
Rev. 1.0 / Dec. 2009
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H5TQ1G43BFR-xxC Даташит, Описание, Даташиты
Revision History
Revision No.
History
0.1 Preliminary Initial Release
0.2 Added IDD Spec
0.3 Package Dimension Notation change - No
Physical change
0.4 Updated IDD Specification
1.0 JEDEC Update
Draft Date
Sep. 2008
Jan. 2009
Apr. 2009
Apr. 2009
Dec. 2009
Remark
Preliminary
http://www.DataSheet4U.com/
Rev. 1.0 / Dec. 2009
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H5TQ1G43BFR-xxC Даташит, Описание, Даташиты
Description
The H5TQ1G43BFR-xxC, H5TQ1G83BFR-xxC and H5tQ1G63BFR-xxC are a 1,073,741,824-bit CMOS Double
Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires
large memory density and high bandwidth. Hynix 1Gb DDR3 SDRAMs offer fully synchronous operations
referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched
on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are
sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched
to achieve very high bandwidth.
Device Features and Ordering Information
FEATURES
• VDD=VDDQ=1.5V +/- 0.075V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK
transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data,
data strobes and data masks latched on the
rising edges of the clock
• Programmable CAS latency 6, 7, 8, 9, 10
supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7
• 8banks
• Average Refresh Cycle (Tcase of0 oC~95oC)
- 7.8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC
• Auto Self Refresh supported
• JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(X16)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
http://www.DataSheet4U.com/
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre-fetch
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
* This product in compliance with the RoHS directive.
Rev. 1.0 / Dec. 2009
3










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Номер в каталогеОписаниеПроизводители
H5TQ1G43BFR-xxC1Gb DDR3 SDRAMHynix Semiconductor
Hynix Semiconductor

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