H5TC1G43TFR-xxA PDF даташит
Спецификация H5TC1G43TFR-xxA изготовлена «Hynix Semiconductor» и имеет функцию, называемую «1Gb DDR3L SDRAM». |
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Детали детали
Номер произв | H5TC1G43TFR-xxA |
Описание | 1Gb DDR3L SDRAM |
Производители | Hynix Semiconductor |
логотип |
31 Pages
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1Gb DDR3L SDRAM
1Gb DDR3L SDRAM
Lead-Free&Halogen-Free
(RoHS Compliant)
H5TC1G43TFR-xxA
H5TC1G83TFR-xxA
http://www.DataSheet4U.com/
*Hynix Semiconductor reserves the right to change products or specifications without notice
Rev. 0.1 / Jan. 2010
1
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Revision History
Revision No.
0.1
History
Initial Release
Draft Date
Jan. 2010
Remark
Preliminary
Rev. 0.1 / Jan. 2010
http://www.DataSheet4U.com/
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Description
The H5TC1G43TFR-xxA and H5TC1G83TFR-xxA are a 1Gb low power Double Data Rate III (DDR3L) Syn-
chronous DRAM, ideally suited for the main memory applications which requires large memory density,
high bandwidth and low power operation at 1.35V. Hynix DDR3L SDRAM provides backward compatibility
with the 1.5V DDR3 based environment without any changes. (Please refer to the SPD information for
details.)
Hynix 1Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of
the clock. While all addresses and control inputs are latched on the rising edges of the clock (falling edges
of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges
of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Device Features and Ordering Information
FEATURES
• VDD=VDDQ=1.35V + 0.100 / - 0.067V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK
transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data,
data strobes and data masks latched on the
rising edges of the clock
• Programmable CAS latency 6, 7, 8, 9, 10
supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7
• 8banks
• Average Refresh Cycle (Tcase of0 oC~95oC)
- 7.8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC
• Auto Self Refresh supported
• JEDEC standard 78ball FBGA(x4/x8)
• Driver strength selected by EMRS
http://www.DataSheet4U.com/
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre-fetch
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
* This product in compliance with the RoHS directive.
Rev. 0.1 / Jan. 2010
3
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Номер в каталоге | Описание | Производители |
H5TC1G43TFR-xxA | 1Gb DDR3L SDRAM | Hynix Semiconductor |
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