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H5TC4G43AFR-xxA PDF даташит

Спецификация H5TC4G43AFR-xxA изготовлена ​​​​«Hynix Semiconductor» и имеет функцию, называемую «4Gb DDR3L SDRAM».

Детали детали

Номер произв H5TC4G43AFR-xxA
Описание 4Gb DDR3L SDRAM
Производители Hynix Semiconductor
логотип Hynix Semiconductor логотип 

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H5TC4G43AFR-xxA Даташит, Описание, Даташиты
4Gb DDR3L SDRAM
4Gb DDR3L SDRAM
Lead-Free&Halogen-Free
(RoHS Compliant)
H5TC4G43AFR-xxA
H5TC4G83AFR-xxA
H5TC4G63AFR-xxA
* SK hynix reserves the right to change products or specifications without notice.
Rev. 1.0 / Apr. 2013
1
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H5TC4G43AFR-xxA Даташит, Описание, Даташиты
Revision History
Revision No.
0.1
1.0
History
Initial Release
1.0 version release
Draft Date
Oct. 2012
Apr. 2013
Remark
Rev. 1.0 / Apr. 2013
2
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H5TC4G43AFR-xxA Даташит, Описание, Даташиты
Description
The H5TC4G43AFR-xxA, H5TC4G83AFR-xxA and H5TC4G63AFR-xxA are a 4Gb low power Double Data Rate
III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large
memory density, high bandwidth and low power operation at 1.35V. DDR3L SDRAM provides backward
compatibility with the 1.5V DDR3 based environment without any changes. (Please refer to the SPD infor-
mation for details.)
4Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the
CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Device Features and Ordering Information
FEATURES
• VDD=VDDQ=1.35V + 0.100 / - 0.067V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• Average Refresh Cycle (Tcase of0 oC~95oC)
- 7.8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC
• On chip DLL align DQ, DQS and DQS transition with CK
transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16
Driver strength selected by EMRS
Dynamic On Die Termination supported
Asynchronous RESET pin supported
ZQ calibration supported
TDQS (Termination Data Strobe) supported (x8 only)
• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13
supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Write Levelization supported
• 8 bit pre-fetch
• This product in compliance with the RoHS directive.
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 8banks
Rev. 1.0 / Apr. 2013
3
Free Datasheet http://www.datasheet4u.com/










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Номер в каталогеОписаниеПроизводители
H5TC4G43AFR-xxA4Gb DDR3L SDRAMHynix Semiconductor
Hynix Semiconductor

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