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H5TQ4G63AFR-xxC PDF даташит

Спецификация H5TQ4G63AFR-xxC изготовлена ​​​​«Hynix Semiconductor» и имеет функцию, называемую «4Gb DDR3 SDRAM».

Детали детали

Номер произв H5TQ4G63AFR-xxC
Описание 4Gb DDR3 SDRAM
Производители Hynix Semiconductor
логотип Hynix Semiconductor логотип 

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H5TQ4G63AFR-xxC Даташит, Описание, Даташиты
4Gb DDR3 SDRAM
4Gb DDR3 SDRAM
Lead-Free&Halogen-Free
(RoHS Compliant)
H5TQ4G43AFR-xxC
H5TQ4G83AFR-xxC
H5TQ4G63AFR-xxC
* SK hynix reserves the right to change products or specifications without notice.
Rev. 1.0 / Apr. 2013
1
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H5TQ4G63AFR-xxC Даташит, Описание, Даташиты
Revision History
Revision No.
0.1
1.0
History
Initial Release
1.0 version release
Draft Date
Oct. 2012
Apr. 2013
Remark
Rev. 1.0 / Apr. 2013
2
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H5TQ4G63AFR-xxC Даташит, Описание, Даташиты
Description
The H5TQ4G43AFR-xxC, H5TQ4G83AFR-xxC and H5TQ4G63AFR-xxC are a 4Gb CMOS Double Data Rate III
(DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory
density and high bandwidth. 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both ris-
ing and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of
the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both ris-
ing and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high
bandwidth.
Device Features and Ordering Information
FEATURES
• VDD=VDDQ=1.5V +/- 0.075V
• 8banks
• Fully differential clock inputs (CK, CK) operation
• Average Refresh Cycle (Tcase of0 oC~95oC)
• Differential Data Strobe (DQS, DQS)
- 7.8 µs at 0oC ~ 85 oC
• On chip DLL align DQ, DQS and DQS transition with CK - 3.9 µs at 85oC ~ 95 oC
transition
• JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
the clock
• ZQ calibration supported
• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13 and
14 supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9,
10
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre-fetch
• This product in compliance with the RoHS directive.
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
Rev. 1.0 / Apr. 2013
3
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