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PDF H5TQ4G43MMR-xxC Data sheet ( Hoja de datos )
| Número de pieza | H5TQ4G43MMR-xxC | |
| Descripción | 4Gb DDR3 SDRAM DDP | |
| Fabricantes | Hynix Semiconductor | |
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H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
4Gb DDR3 SDRAM DDP(2Gbx2)
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Rev. 0.1 / Aug 2008
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
1
Free Datasheet http://www.datasheet4u.com/
1 page  
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
DESCRIPTION
The H5TQ4G43MMR-xxX and H5TQ4G83MMR-xxX are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchro-
nous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
Hynix 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data
strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
1.1 Device Features and Ordering Information
. FEATURES
• VDD=VDDQ=1.5V +/- 0.075V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK
transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data,
data strobes and data masks latched on the
rising edges of the clock
• Programmable CAS latency 6, 7, 8, 9 and (10)
supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 8banks
• 8K refresh cycles /64ms
• JEDEC standard 82ball FBGA(x4/x8)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• Auto Self Refresh supported
• On Die Thermal Sensor supported (JEDEC optional)
• 8 bit pre-fetch
. ORDERING INFORMATION
Part No.
H5TQ4G43MMR-xx*X
H5TQ4G83MMR-xx*X
Configuration
512M x 4
256M x 8
Package
82ball FBGA
* xx means Binning grade (Speed/IDD...)
* X means Power Consumption & Temperature
. OPERATING FREQUENCY
Grade
-S6
-G7
CL5
O
Frequency [MHz]
CL6 CL7 CL8 CL9 CL10
Remark
(CL-tRCD-tRP)
O
O OO
DDR3-800 6-6-6
DDR3-1066 7-7-7
Rev. 0.1 /Aug 2008
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
2. Command Description
2.1 Command Truth Table
(a) note 1,2,3,4 apply to the entire Command Truth Table
(b) Note 5 applies to all Read/Write command
[BA = Bank Address, RA = Rank Address, CA = Column Address, BC = Burst Chop, X = Don’t Care, V = Valid]
Function
CKE
Abbrev
iation
Previ
ous
Curre
nt
Cycle Cycle
CS
Mode Register Set
Refresh
Self Refresh Entry
MRS
REF
SRE
Self Refresh Exit
SRX
Single Bank Precharge PRE
Precharge all Banks PREA
Bank Activate
ACT
Write (Fixed BL8 or BC4) WR
Write (BC4, on the Fly) WRS4
Write (BL8, on the Fly) WRS8
Write with Auto
Precharge
(Fixed BL8 or BC4)
WRA
Write with Auto
Precharge
(BC4, on the Fly)
WRAS
4
Write with Auto
Precharge
(BL8, on the Fly)
WRAS
8
Read (Fixed BL8 or BC4) RD
Read (BC4, on the Fly) RDS4
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
HL
HL
LL
H
H
L
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
HL
Read (BL8, on the Fly)
Read with Auto
Precharge
(Fixed BL8 or BC4)
Read with Auto
Precharge
(BC4, on the Fly)
Read with Auto
Precharge
(BL8, on the Fly)
No Operation
Device Deselected
RDS8
RDA
RDAS4
RDAS8
NOP
DES
Power Down Entry
PDE
H
H
H
H
H
H
H
HL
HL
HL
HL
HL
HH
L
L
H
RAS
L
L
L
V
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
V
CAS
L
L
L
V
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
X
H
V
WE
BA0- A13- A12- A10-
BA3 A15 BC AP
A0-
A9,
A11
Notes
L BA
OP Code
HVVV VV
H V V V V V 7,9,12
V
H
V
V
V
V
V
7,8,9,1
2
L BA V V L V
LVVV HV
H BA
Row Address (RA)
L BA RFU V L CA
L BA RFU L L CA
L BA RFU H L CA
L BA RFU V H CA
L BA RFU L H CA
L BA RFU H
H BA RFU V
H BA RFU L
H BA RFU H
H BA RFU V
H CA
L CA
L CA
L CA
H CA
H BA RFU L H CA
H BA RFU H
HVVV
XXXX
H
VVV
V
H CA
V V 10
X X 11
V V 6,12
Rev. 0.1 /Aug 2008
11
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