PDF HMT325U7EFR8A Data sheet ( Hoja de datos )

Número de pieza	HMT325U7EFR8A
Descripción	DDR3L SDRAM
Fabricantes	Hynix Semiconductor
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No Preview Available ! 240pin DDR3L SDRAM Unbuffered DIMM DDR3L SDRAM Unbuffered DIMMs Based on 2Gb E-Die HMT325U7EFR8A HMT351U7EFR8A SK hynix reserves the right to change products or specifications without notice. Rev. 1.3 / Jul. 2013 1 Free Datasheet http://www.datasheet4u.com/ 1 page Pin Descriptions Pin Name Description Pin Name Description A0–A15 BA0–BA2 RAS CAS WE S0–S1 CKE0–CKE1 ODT0–ODT1 DQ0–DQ63 CB0–CB7 DQS0–DQS8 DQS0–DQS8 DM0–DM8 CK0–CK1 CK0–CK1 SDRAM address bus SDRAM bank select SDRAM row address strobe SDRAM column address strobe SDRAM write enable DIMM Rank Select Lines SDRAM clock enable lines On-die termination control lines DIMM memory data bus DIMM ECC check bits SDRAM data strobes (positive line of differential pair) SDRAM data strobes (negative line of differential pair) SDRAM data masks/high data strobes (x8-based x72 DIMMs) SDRAM clocks (positive line of differential pair) SDRAM clocks (negative line of differential pair) SCL SDA SA0–SA2 VDD VDDQ* VREFDQ VREFCA VSS VDDSPD NC TEST RESET VTT RSVD - I2C serial bus clock for EEPROM I2C serial bus data line for EEPROM I2C slave address select for EEPROM SDRAM core power supply SDRAM I/O Driver power supply SDRAM I/O reference supply SDRAM command/address reference supply Power supply return (ground) Serial EEPROM positive power supply Spare pins (no connect) Memory bus analysis tools (unused on memory DIMMS) Set DRAMs to Known State SDRAM I/O termination supply Reserved for future use - *The VDD and VDDQ pins are tied common to a single power-plane on these designs Rev. 1.3 / Jul. 2013 5 Free Datasheet http://www.datasheet4u.com/ 5 Page Functional Block Diagram 2GB, 256Mx72 Module(1Rank of x8) DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 DQS8 DQS8 DM8 BA0–BA2 A0–A15 RAS CAS CKE0 WE ODT0 CK0 CK0 RESET S0 DM CS DQS DQS DQ0 I/O 0 DQ1 I/O 1 D0 DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 ZQ DQ7 I/O 7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D1 ZQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D2 ZQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D3 ZQ DQS4 DQS4 DM4 DQS5 DQS5 DM5 DQS6 DQS6 DM6 DQS7 DQS7 DM7 CB0 DM I/O 0 CS DQS DQS SCL SPD(TS integrated) CB1 I/O 1 D8 CB2 I/O 2 CB3 I/O 3 EVENT EVENT A0 A1 A2 CB4 I/O 4 CB5 I/O 5 CB6 I/O 6 ZQ SA0 SA1 SA2 CB7 I/O 7 BA0–BA2: SDRAMs D0–D8 A0–A15: SDRAMs D0–D8 VDDSPD RAS: SDRAMs D0–D8 CAS: SDRAMs D0–D8 VDD/VDDQ CKE: SDRAMs D0–D8 WE: SDRAMs D0–D8 ODT: SDRAMs D0–D8 VREFDQ VSS CK: SDRAMs D0–D8 CK: SDRAMs D0–D8 VREFCA RESET: SDRAMs D0-D8 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D4 ZQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D5 ZQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D6 ZQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D7 ZQ Notes: 1. DQ-to-I/O wiring is shown as recom- SDA mended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S rela- tionships must be maintained as shown. 3. DQ,CB,DM,DQS/DQS resistors;Refer to associated topology diagram. 4. Refer to the appropriate clock wiring SPD D0–D8 topology under the DIMM wiring details section of this document. 5. For each DRAM, a unique ZQ resistor D0–D8 D0–D8 is connected to ground.The ZQ resis- tor is 240ohm+-1% 6. One SPD exists per module. D0–D8 Rev. 1.3 / Jul. 2013 11 Free Datasheet http://www.datasheet4u.com/ 11 Page

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