CAV24C16 PDF даташит
Спецификация CAV24C16 изготовлена «ON Semiconductor» и имеет функцию, называемую «(CAV24C02 - CAV24C16) I2C CMOS Serial EEPROM». |
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Детали детали
Номер произв | CAV24C16 |
Описание | (CAV24C02 - CAV24C16) I2C CMOS Serial EEPROM |
Производители | ON Semiconductor |
логотип |
15 Pages
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CAV24C02, CAV24C04,
CAV24C08, CAV24C16
2-Kb, 4-Kb, 8-Kb and 16-Kb
I2C CMOS Serial EEPROM
Description
The CAV24C02/04/08/16 are 2−Kb, 4−Kb, 8−Kb and 16−Kb
respectively CMOS Serial EEPROM devices organized internally as
16/32/64 and 128 pages respectively of 16 bytes each. All devices
support both the Standard (100 kHz) as well as Fast (400 kHz) I2C
protocol.
Data is written by providing a starting address, then loading 1 to 16
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address up to eight
CAV24C02, four CAV24C04, two CAV24C08 and one CAV24C16
device on the same bus.
Features
• Automotive Temperature Grade 1 (−40°C to +125°C)
• Supports Standard and Fast I2C Protocol
• 2.5 V to 5.5 V Supply Voltage Range
• 16−Byte Page Write Buffer
• Hardware Write Protection for Entire Memory
• CAV Prefix for Automotive and Other Applications Requiring Site
and Change Control
• Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
• Low power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
VCC
SCL
A2, A1, A0
WP
CAV24Cxx
SDA
VSS
Figure 1. Functional Symbol
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
www.onsemi.com
TSSOP−8
Y SUFFIX
CASE 948AL
SOIC−8
W SUFFIX
CASE 751BD
WLCSP−4***
C4A SUFFIX
CASE 567DC
WLCSP−5***
C5A SUFFIX
CASE 567DD
PIN CONFIGURATIONS
SOIC (W), TSSOP (Y)
CAV24C__
16 / 08 / 04 / 02
NC / NC / NC / A0
NC / NC / A1 / A1
NC / A2 / A2 / A2
VSS
18
27
36
45
(Top View)
Pin 1 1
2 Pin 1 1 2
VCC
WP
SCL
SDA
3
A VCC
VSS
B SCL SDA
VCC
VSS
SDA
A
B
WP SCL C
WLCSP−4***
WLCSP−5***
(Top Views)
PIN FUNCTION
Pin Name
A0, A1, A2
Function
Device Address Input
SDA
Serial Data Input/Output
SCL Serial Clock Input
WP Write Protect Input
VCC Power Supply
VSS Ground
NC No Connect
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 4
1
Publication Order Number:
CAV24C02/D
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CAV24C02, CAV24C04, CAV24C08, CAV24C16
(TSSOP−8)
DEVICE MARKINGS
(SOIC−8)
CSSS
AYMXXX
G
CSSS
SSS
SSS
SSS
SSS
A
Y
M
XXX
G
= Specific Device Code, where
= 02H for CAV24C02
= 04K for CAV24C04
= 08K for CAV24C08
= 16K for CAV24C16
= Assembly Location
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
= Last Three Digits of Assembly Lot Number
= Pb−Free Package
24CSSS
AYMXXX
G
24CSSS = Specific Device Code, where
SSS = 02H for CAV24C02
SSS = 04K for CAV24C04
SSS = 08K for CAV24C08
SSS = 16K for CAV24C16
A = Assembly Location
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
G = Pb−Free Package
Pin 1 TOP MARKING FOR WLCSP Pin 1
(Ball Down)
X
YM
WLCSP−4
X = Specific Device
X = Code
4 = 24C04
8 = 24C08
6 = 24C16
X
YM
WLCSP−5
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
−65 to +150
°C
Voltage on any pin with respect to Ground (Note 1)
−0.5 to +6.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. During input transitions, voltage undershoot on any pin should not exceed −1 V for more than 20 ns. Voltage overshoot on pins A0, A1, A2
and WP should not exceed VCC + 1 V for more than 20 ns, while voltage on the I2C bus pins, SCL and SDA, should not exceed the absolute
maximum ratings, irrespective of VCC.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
Min Units
NEND (Note 3)
Endurance
1,000,000
Program / Erase Cycles
TDR Data Retention
100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.
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CAV24C02, CAV24C04, CAV24C08, CAV24C16
Table 3. D.C. OPERATING CHARACTERISTICS
(VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min Max Units
ICCR Read Current
Read, fSCL = 400 kHz
1 mA
ICCW Write Current
Write, fSCL = 400 kHz
2 mA
ISB Standby Current
All I/O Pins at GND or VCC
TA = −40°C to +125°C
5 mA
IL I/O Pin Leakage
Pin at GND or VCC
2 mA
VIL Input Low Voltage
−0.5
0.3 x VCC
V
VIH Input High Voltage
A0, A1, A2 and WP
0.7 x VCC
VCC + 0.5
V
SCL and SDA
0.7 x VCC
5.5
V
VOL Output Low Voltage
VCC > 2.5 V, IOL = 3 mA
0.4 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max Units
CIN (Note 4)
SDA Pin Capacitance
Other Pins
VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V
8 pF
6 pF
IWP (Note 5)
WP Input Current
VIN < VIH, VCC = 5.5 V
130 mA
VIN < VIH, VCC = 3.6 V
120
VIN < VIH, VCC = 2.5 V
80
VIN > VIH
2
IA (Note 5)
Address Input Current
(A0, A1, A2)
VIN < VIH, VCC = 5.5 V
VIN < VIH, VCC = 3.6 V
50 mA
35
VIN < VIH, VCC = 2.5 V
25
VIN > VIH
2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.
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