NCP590 PDF даташит
Спецификация NCP590 изготовлена «ON Semiconductor» и имеет функцию, называемую «Ultra Low Dropout CMOS LDO». |
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Детали детали
Номер произв | NCP590 |
Описание | Ultra Low Dropout CMOS LDO |
Производители | ON Semiconductor |
логотип |
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NCP590
Dual Output, High Accuracy,
Ultra Low Dropout
CMOS LDO
The NCP590 is a family of very high precision dual-output CMOS
LDOs offered in a 2x2 DFN8 package. Each output is capable of
delivering up to 300 mA and is available in voltages from 0.8 V to
5 V.
The set point output voltage is accurate to within ±0.9% with an
operating voltage input up to 5.5 V. With its ultra low dropout
characteristics and low quiescent and ground current consumption,
the NCP590 is ideal for all battery operated consumer and
microprocessor applications. The NCP590 is protected against short
circuit and thermal overload conditions.
Features
•ăDual Outputs, Each Supporting up to 300 mA Current
•ăAvailable in Output Combinations Ranging from 0.8 V to 5.0 V
•ă2.1 V to 5.5 V VCC Operating Supply Range
•ăUltra-High Accuracy (0.9% max at 100 mA load & 25°C)
•ăEach Output has a Dedicated Enable Control Pin
•ăEnable Threshold Supports sub-1 V Systems
•ăVery Low Drop Out Voltage (50 mV typ @ 100 mA load)
•ăLow Noise (~20 mVrms) without Bypass Capacitor
•ăUltra Low Shutdown Current (0.2 mA)
•ăLow Quiescent and Ground Current (80 - 100 mA typ.)
•ăThermal Shutdown and Current Limit Protection
•ăActive Output Discharge when Disabled
•ăNo Minimum Output Current Required for Stability
•ăRequires Cout of only 1.0 mF (any ESR) for Stability
•ăStable with Any Type of Capacitor (including MLCC) and Zero Load
•ăInput Under Voltage Lock Out (UVLO)
•ăInternally Compensated Regulator for Quick Transient Response
•ăSpace-Ef ficient 2x2 DFN8 Package
•ăThis is a Pb-Free Device
Applications
•ăCellular Phones
•ăCameras
•ăMP3/CD Players, PDA's, Camcorders
•ăDSP Supplies
•ăPortable Info-tronics
•ăPCMCIA Cards
•ăNetworking Systems, DSL/Cable Modems
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1
DFN8, 2x2
MN SUFFIX
CASE 506AA
MARKING DIAGRAM
14
XX = Specific Device Code
M = Date Code
PIN CONNECTIONS
Vin 1
EN1 2
EN2 3
NC 4
(Top View)
8 Vout1
7 Vout2
6 GND
5 NC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
©Ă Semiconductor Components Industries, LLC, 2007
June, 2007 - Rev. 0
1
Publication Order Number:
NCP590/D
Free Datasheet http://www.datasheet4u.com/
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NCP590
Vin
Cin
1 mF
OFF ON
OFF ON
Vin Vout1
NCP590
EN1
Vout2
EN2 GND
NC NC
Cout1
1 mF
Cout2
1 mF
Figure 1. Typical Application
Vout1
RLoad
Vout2
RLoad
PIN FUNCTION
Pin No.
1
2
3
4, 5
6
PAD
7
8
Symbol
Vin
EN1
EN2
NC
GND
GND
Vout2
Vout1
Function
Input; Bypass directly at the IC with a 1 mF ceramic capacitor to Ground
Enable for output regulator 1; raise above 0.95 V to enable Vout1
Enable for output regulator 2; raise above 0.95 V to enable Vout2
NC; Do not make connection to these pins
Ground
The thermal pad should be connected to ground for best thermal performance. Float if necessary
Output 2; Bypass to GND with a capacitor, 4.7 mF ≥ C ≥ 0.7 mF, any ESR
Output 1; Bypass to GND with a capacitor, 4.7 mF ≥ C ≥ 0.7 mF, any ESR
Vin
EN1
EN2
Programmable
Reference
Error
Amplifier
-
+
Current Limit
Saturation Sense
Thermal Protection
Error
Amplifier
-
+
Current Limit
Saturation Sense
Thermal Protection
Vout1
Vout2
GND
Figure 2. Block Diagram
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NCP590
ABSOLUTE MAXIMUM RATINGS TJ = -40°C to 125°C
Pin Symbol, Parameter
Symbol
Condition
Min Max Unit
VIN, Input to regulator
Voltage
Current
VIN
IIN
-0.3 6.0 V
- Internally
Limited
VIN, Input peak Transient Voltage to regulator wrt GND
VOUT1, VOUT2,
Regulated Output
Voltage
VIN
VOUT
7.0 V
-0.3 VIN + 0.3 V
or 6.0
(Note 1)
Current
IOUT
- Internally
Limited
EN1, EN2, Enable Input
VEN -0.3 VIN + 0.3 V
or 6.0
(Note 1)
Junction Temperature
Storage Temperature
TJ - 125 _C
Tstg -50 150
ESD Capability, Human body model (Note 3)
ESDHB
-2 2 kV
ESD Capability, Machine model (Note 3)
ESDMM
-200
200
V
Voutx-V in (Note 2)
VRB - 0.3 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Which ever limit is lower
2. Exceeding this value will turn on the body diode of the PMOS driver (reference Figure 2).
THERMAL RESISTANCE
Parameter
Symbol
Condition
Junction-to-Ambient
2X2 DFN
1 oz Cu
qJA 207.0 sq mm 1 oz Cu
54.2 sq mm 1 oz Cu
20.2 sq mm 1 oz Cu
Junction-to-Ambient
2X2 DFN
2 oz Cu
qJA 207.0 sq mm 2 oz Cu
54.2 sq mm 2 oz Cu
20.2 sq mm 2 oz Cu
Junction-to-Board
Lead Temperature Soldering, (Note 4)
Reflow (SMD styles only), lead free
2X2 DFN
PsiJB
Tsld
60 -150 sec above 217
40 sec max at peak
Moisture Sensitivity Level
MSL
3. This device series incorporates ESD protection and is tested by the following methods:
ąESD HBM tested per AEC-Q100-002 (EIA/JESD22-A114)
ąESD MM tested per AEC-Q100-003 (EIA/JESD22-A115)
4. Per IPC/JEDEC J-STD-020C
Value
158
210
375
133
184
330
36.4
265 pk
Unit
_C/W
_C/W
_C/W
_C
3
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3
Free Datasheet http://www.datasheet4u.com/
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