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PDF SAM9G25 Data sheet ( Hoja de datos )
| Número de pieza | SAM9G25 | |
| Descripción | SMART ARM-based Embedded MPU | |
| Fabricantes | ATMEL Corporation | |
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SAM9G25
Atmel | SMART ARM-based Embedded MPU
DATASHEET
Description
The SAM9G25 is a member of the Atmel® | SMART series of 400 MHz
ARM926EJ-S™ embedded microprocessor units. This MPU features connectivity
peripherals, a high data bandwidth architecture and a small footprint package
option, making it an optimized solution for industrial applications.
The SAM9G25 interface peripherals include a camera interface that supports
direct connection to the ITU-R BT. 601/656 8-bit mode compliant sensors and up
to 12-bit grayscale sensors. Communication peripherals include a soft modem
supporting exclusively the Conexant SmartDAA line driver, HS (480 Mbps) USB
Host and Device ports with on-chip transceivers, FS USB Host, 10/100 Ethernet
MAC, two HS SDCard/SDIO/MMC interfaces, USARTs, SPIs, I2S, multiple TWIs
and 10-bit ADC.
The multi-layer bus matrix is linked to 2 x 8 DMA channels as well as DMAs
dedicated to the communication and interface peripherals, ensuring uninterrupted
data transfers with minimal processor overhead.
The External Bus Interface incorporates controllers for 4-bank and 8-bank
DDR2/LPDDR, SDRAM/LPSDRAM, static memories, as well as specific circuitry
for MLC/SLC NAND Flash with integrated ECC up to 24 bits.
The SAM9G25 is available in a 217-ball BGA package with 0.8 mm ball pitch, as
well as in 247-ball TFBGA and 247-ball VFBGA packages with 0.5 mm ball pitch,
making it ideally suited for space-constrained applications.
Atmel-11032G-ATARM-SAM9G25-Datasheet_31-Aug-15
1 page  
2. Signal Description
Table 2-1 gives details on the signal name classified by peripheral.
Table 2-1. Signal Description List
Signal Name
XIN
XOUT
XIN32
XOUT32
VBG
PCK0–PCK1
SHDN
WKUP
TCK
TDI
TDO
TMS
JTAGSEL
RTCK
NRST
TST
NTRST
BMS
DRXD
DTXD
IRQ
FIQ
PA0–PA31
PB0–PB18
PC0–PC31
PD0–PD21
Function
Clocks, Oscillators and PLLs
Main Oscillator Input
Main Oscillator Output
Slow Clock Oscillator Input
Slow Clock Oscillator Output
Bias Voltage Reference for USB
Programmable Clock Output
Shutdown, Wakeup Logic
Shutdown Control
Wake-Up Input
ICE and JTAG
Test Clock
Test Data In
Test Data Out
Test Mode Select
JTAG Selection
Return Test Clock
Reset/Test
Microcontroller Reset
Test Mode Select
Test Reset Signal
Boot Mode Select
Debug Unit - DBGU
Debug Receive Data
Debug Transmit Data
Advanced Interrupt Controller - AIC
External Interrupt Input
Fast Interrupt Input
PIO Controller - PIOA - PIOB - PIOC - PIOD
Parallel IO Controller A
Parallel IO Controller B
Parallel IO Controller C
Parallel IO Controller D
Type
Input
Output
Input
Output
Analog
Output
Output
Input
Input
Input
Output
Input
Input
Output
I/O
Input
Input
Input
Input
Output
Input
Input
I/O
I/O
I/O
I/O
Active Level
Low
SAM9G25 [DATASHEET]
Atmel-11032G-ATARM-SAM9G25-Datasheet_31-Aug-15
5
5 Page 
Table 3-2.
I/O Type
USBFS
USBHS
VBG
I/O Type Assignment and Frequency (Continued)
I/O Frequency Charge Load
(MHz)
(pF) Output Current Signal Name
12 10
HFSDPA, HFSDPB/DFSDP, HFSDPC, HFSDMA,
HFSDMB/DFSDM, HFSDMC
480 10
HHSDPA, HHSDPB/DHSDP, HHSDMA, HHSDMB/DHSDM
0.25 10
VBG
3.3.1
Reset State
In the tables that follow, the column “Reset State” indicates the reset state of the line with mnemonics.
“PIO” “/” signal
Indicates whether the PIO Line resets in I/O mode or in peripheral mode. If “PIO” is mentioned, the PIO Line is
maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in
the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this function and the
corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address
lines, which require the pin to be driven as soon as the reset is released.
“I”/“O”
Indicates whether the signal is input or output state.
“PU”/“PD”
Indicates whether Pull-Up, Pull-Down or nothing is enabled.
“ST”
Indicates if Schmitt Trigger is enabled.
Example:
The PB18 “Reset State” column shows “PIO, I, PU, ST”. That means the line PIO18 is configured as
an Input with Pull-Up and Schmitt Trigger enabled. PD14 reset state is “PIO, I, PU”. That means PIO
Input with Pull-Up. PD15 reset state is “A20, O, PD” which means output address line 20 with Pull-
Down.
SAM9G25 [DATASHEET]
Atmel-11032G-ATARM-SAM9G25-Datasheet_31-Aug-15
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAM9G25.PDF ] | |
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