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PDF SD60C52P Data sheet ( Hoja de datos )
| Número de pieza | SD60C52P | |
| Descripción | (SD60C32 / SD60C52) CMOS SINGLE-COMPONENT 8-BIT MICROCOMPUTER | |
| Fabricantes | AUK | |
| Logotipo |  |
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Semiconductor
SD60C32/P, SD60C52/P
CMOS SINGLE-COMPONENT 8-BIT MICROCOMPUTER
Description
The AUK 60C32/P 60C52/P is a high-performance micro controller fabricated with AUK
high-density CMOS technology. The AUK CMOS technology combines the high speed and
density characteristics of MOS with the low power attributes of CMOS.
The 60C52 contains a 8K×8 ROM, a 256×8 RAM, 32 I/O lines, three 16bit counter/timers,
a six sourc two-priority level nested interrupt structure, a serial I/O port for either multi-
processor communication, I/O expansion or full duplex UART, and on-chip oscillator and
clock circuits.
In addition, the device has two software selectable modes of power reduction idle mode
and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers,
serial port, and interrupt system to continue functioning.
The power-down mode saves the RAM contents but freezes the oscillator , causing all other
chip function to be inoperative.
Features
• 8-bit CPU optimized for control applications.
• MCS-51 fully compatible instruction set
• Pin-to-pin compatible with intel's 80C52/80C32.
• 256 Bytes of on-chip data RAM.
• 60C52 low power CPU only.
• ONCETM (ON-circuit emulation) mode
• Power control modes
-Idle mode
• 32 programmable I/O lines.
-Power down mode
• Three 16bit timer/counters.
• 6 interrupt source
• TTL and CMOS compatible logic levels
• 64K external program memory space and data memory space.
Ordering Information
Type NO. Marking
SD60C32 SD60C32
SD60C52 SD60C52
Package Code
PLCC44
PLCC44
Type NO.
SD60C32P
SD60C52P
Marking
SD60C32
SD60C52
Package Code
DIP40
DIP40
Outline Dimensions
unit : mm
PLCC44
KSI-W015-000
DIP40
1
Free Datasheet http://www.datasheet4u.com/
1 page  
SD60C32/P SD60C52/P
RST: PIN 9 (DIP40), PIN 10 (PLCC44)
Reset input. A high on this pin for two machine cycles while the oscillator is running
resets the device. An internal pulldown resistor permits a power-on reset with
only a capacitor connected to VCC.
ALE: PIN 30 (DIP40), PIN 33 (PLCC44)
Address latch enable output pulse for latching the low byte of the address
during accesses to external memory.
In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency,
and may be used for external timing or clocking purposes.
Note : However, that one ALE pulse is skipped during each access to external
data memory.
This pin is also the program pulse input PROG during EPROM programming.
PSEN : PIN 29 (DIP 40), PIN 32 (PLCC44)
Program store enable is the read strobe to external program memory. When the 60C52
is executing code from external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external
data memory. PSEN is not activated during fetches from internal program memory.
EA: PIN 31 (DIP 40), PIN 35 (PLCC44)
External access enable. EA must be strapped to VSS in order to enable the device
to fetch code from external program memory locations starting at 0000H up to FFFFH.
If EA is strapped to VCC the device executes from internal program memory unless
the program counter contains an address greater than 0FFFH.
XTAL1: PIN 19 (DIP 40), PIN 21 (PLCC44)
Input to the Inverting oscillator amplifier and input to the internal clock generator circuits.
XTAL2: PIN 18 (DIP 40), PIN 20 (PLCC44)
Output from the inverting oscillator amplifier
0 Crystal Oscillator
NC: PIN1, 12, 23, 34 (PLCC44)
Non connection pins.
KSI-W015-000
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
Timing Diagram (Continued)
SD60C32/P SD60C52/P
KSI-W015-000
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet SD60C52P.PDF ] | |
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