NCP1901 PDF даташит
Спецификация NCP1901 изготовлена «ON Semiconductor» и имеет функцию, называемую «Primary Side Combination Resonant and PFC Controllers». |
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Детали детали
Номер произв | NCP1901 |
Описание | Primary Side Combination Resonant and PFC Controllers |
Производители | ON Semiconductor |
логотип |
13 Pages
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NCP1901
Advance Information
Primary Side Combination
Resonant and PFC
Controllers
The NCP1901 is a combination of PFC and half−bridge
resonant controllers optimized for off−line adapter
applications. This device includes all the features needed
to implement a highly efficient and small form factor
adapter. It integrates a critical conduction mode (CrM)
power factor correction (PFC) controller and a half−bridge
controller with a built−in 600 V driver. The half−bridge
stage operates at a fixed frequency. Regulation is achieved
by adjusting the PFC stage output voltage.
This device includes an enable input on the PFC
feedback pin, open feedback loop protection and PFC
overvoltage and undervoltage detectors. Other features
included in the NCP1901 are a 600 V startup circuit and an
adjustable frequency oscillator. The controllers are properly
sequenced, simplifying system design.
Features
• Adjustable Half−Bridge Frequency up to 75 kHz
• Open Feedback Loop Protection
• CrM Power Factor Correction Controller
• PFC Undervoltage Detector
• PFC Overvoltage Detector
• Half−Bridge Controller with 600 V High Side Gate
Drive
• State Machine Ensures Proper Turn−on and Turn−off
of Half−Bridge Stage
• Enable Input on the PFC Feedback Pin Disables
Controllers and Reduces Power
• Controllers are Properly Sequenced for Fault Free
Operation
• Internal 600 V Startup Circuit
• This is a Pb−Free Device
Typical Applications
• High Efficiency Notebook Adapter
• Solid State Lighting
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
http://onsemi.com
SO−20 WB
DW SUFFIX
CASE 751D
SOIC−16
D SUFFIX
CASE 751B
MARKING
DIAGRAM
16
NCP1901G
AWLYWW
1
20
NCP1901
AWLYYWWG
1
NCP1901 = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y or YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
NCP1901DR2G
NCP1901DWR2G
SOIC−16
(Pb−Free)
SO−20 WB
(Pb−Free)
2500/Tape & Reel
1000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2009
February, 2009 − Rev. P0
1
Publication Order Number:
NCP1901/D
Free Datasheet http://www.datasheet4u.com/
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SO−20 WB
HV 1
NC 2
NC 3
OSC 4
GND 5
VREF 6
PFB 7
PCS 8
PZCD 9
PControl 10
NCP1901
20 HBoost
19 HDRVhi
18 HVS
17 NC
16 NC
15 HDRVlo
14 PDRV
13 PGND
12 VCC
11 PCT
HV
OSC
GND
VREF
PFB
PCS
PZCD
PControl
Figure 1. Pin Connections
SOIC−16
1
HBoost
HDRVhi
HVS
HDRVlo
PDRV
PGND
VCC
PCT
PDRV
VCC
PZCD
PControl
VDD
> 5.65 V
Clamp
PFB
< 2.25 V
Clamp
PFC
Error
Amplifier
IPFB
VDD
+
− VPREF
PCT
IPCT(C)
Level
Shifter
ZCD
Comparator
UVLO
+
VZCD
SQ
Dominant
Reset
Latch
RQ
VCC
Good
On time
Comparator
PFC OVP
Comparator
Level
Shifter
Pulse
Trigger
Delay
HV
VCC
Management
Istart
+
−
+ VCC(on)/
−
VCC(off)/
UVLO
Undervoltage
Detector
S
Dominant
Reset
Latch
Q
R
VCC
VCC
CCC
HBoost
HDRVhi
HVS
Dboost
Cboost
HDRVlo
Delay
VDD GND
+
PFC UVP
Comparator
VPOVP−
+
VPUVP−
VCCGood
QQ
Clock
CLK
Q
Q
Enable
CLK +
−
5V/
3V
+
−
IOSC(C)
OSC
4*IOSC(C)
PCS
LEB
+
−
ComPCpaSrator
VPCS(ILIM)
PDRV
UVLO
SQ
R
VDD
Voltage
Reference
VREF
Figure 2. Functional Block Diagram
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2
Free Datasheet http://www.datasheet4u.com/
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NCP1901
Table 1. PIN FUNCTION DESCRIPTION
20 Pin 16 Pin
Name
Description
1 1 HV This is the input of the high voltage startup regulator and connects directly to the bulk voltage. A
constant current source supplies current from this pin to the VCC capacitor, eliminating the need for
an external startup resistor. The charge current is 7.5 mA (typical).
4
2
OSC
A capacitor on this pin adjusts the frequency of the internal oscillator. The oscillator sets the fre-
quency of the half−bridge controller. The half−bridge operates at half the oscillator frequency.
5
3
GND
Analog ground.
6
4
VREF
Reference voltage. The capacitor on this pin decouples the internal reference. A 0.1 mF capacitor
needs to be connected between this pin and ground.
7 5 PFB PFC voltage feedback input. The voltage on this pin is compared to a 2.5 V reference (typical) to
regulate the PFC output voltage. The voltage on this pin is also used to detect PFC undervoltage
and overvoltage conditions.
8
6
PCS
PFC regulator current sense input. A voltage ramp proportional to the PFC switch current is applied
to this pin. The current sense threshold, VPCS(ILIM), is typically 0.84 V. A 110 ns (typical) leading
edge blanking circuit filters the current sense signal at the start of each cycle.
9
7
PZCD
PFC inductor zero current detector. The inductor current is monitored using an auxiliary winding on
the PFC inductor. The PFC drive signal is enabled during a high to low transition on the PZCD pin.
A series resistor limits the current into the PZCD pin.
10 8 PControl PFC control voltage. This pin connects to the output of the PFC error amplifier. The error amplifier is
a transconductance amplifier. A compensation network between this pin and grounds sets the PFC
loop bandwidth. The PFC control voltage is compared to a level shifted version of VPCT to control
the PFC duty ratio.
11
9
PCT
PFC on time control capacitor. A 270 mA (typical) current source charges a capacitor connected
between this pin and ground. Once the level shifted PCT voltage reaches VPControl, the PFC drive
signal is disabled and the PCT capacitor is discharged.
12
10
VCC
Positive input supply. This pin connects to an external capacitor for energy storage. An internal
current source supplies current from HV to this pin. Once the VCC voltage reaches VCC(on) (15.3 V
typical), the current source turns off and the controller is enabled. The current source turns on once
VCC falls to VCC(off) (9.3 V typical). During normal operation, power is supplied to the IC via this pin
by means of an auxiliary winding.
13
11
PGND
Ground connection for PDRV and HDRVlo. Tie to the power stage return with a short trace.
14
12
PDRV
PFC switch gate drive control signal. The source and sink drive capability is limited to 60 W and 15
W (typical), respectively. A discrete driver may be needed to drive the external MOSFET.
15 13 HDRVlo Half−bridge low side switch gate drive control signal. The source and sink drive capability is limited
to 75 W and 15 W (typical), respectively. A discrete driver may be needed to drive the half bridge
switch.
18
14
HVS
Half−bridge high side driver source connection. This pin connects directly to the bridge terminal and
can float up to 600 V.
19 15 HDRVhi Half−bridge high side switch gate drive control signal. The source and sink drive capability is limited
to 75 W and 15 W (typical), respectively. The supply terminals of the high side driver connect to the
HBoost and HVS pins.
20 16 HBoost Supply voltage of the high side gate driver. A charge pump generates a bootstrap voltage floating on
top of the HVS voltage. A diode between the VCC and HBoost pins provides a charge path. The
bootstrap voltage is VCC minus a diode drop.
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3
Free Datasheet http://www.datasheet4u.com/
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NCP1901 | Primary Side Combination Resonant and PFC Controllers | ON Semiconductor |
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