PDF NCP1910 Data sheet ( Hoja de datos )

Número de pieza	NCP1910
Descripción	High Performance Combo Controller
Fabricantes	ON Semiconductor
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No Preview Available ! NCP1910 High Performance Combo Controller for ATX Power Supplies Housed in a SO−24WB package, the NCP1910 combines a state−of−the−art circuitry aimed to powering next generation of ATX or flat TVs converters. With a 65 kHz Continuous Conduction Mode Power Factor Controller and a LLC controller hosting a high−voltage driver, the NCP1910 is ready to power 85+ types of offline power supplies. To satisfy stringent efficiency considerations, the PFC circuit implements an adjustable frequency fold back to reduce switching losses as the load is going light. To cope with all the signal sequencing required by the ATX and flat TVs specifications, the controller includes several dedicated pins enabling handshake between the secondary and the primary sides. These signals include a power−good line but also a control pin which turns the controller on and off via an opto coupler. Safety−wise, a second OVP input offers the necessary redundancy in case the main feedback network would drift away. Finally, a fast fault input immediately reacts in presence of an over current condition by triggering an auto−recovery soft−start sequence. http://onsemi.com SO−24WB Less Pin 21 DW SUFFIX CASE 752AB MARKING DIAGRAM NCP1910XXX AWLYYWWG 1 Features • Fixed−Frequency 65 kHz CCM Power Factor Controller • Average Current−Mode Control for Low Line Distortion XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package • Dynamic Response Enhancer Reduces Bulk Undershoot • Independent Over Voltage Protection Sensing Pin with Latch−off Capability ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 36 of this data sheet. • Adjustable Frequency Fold Back Improves Light Load Efficiency • Adjustable Line Brown−out Protection with 50 ms Delay to Help Meeting Hold−up Time Specifications • on/off Control Pin for Secondary−Based Remote Control • Programmable Over current Threshold Leads to an Optimized Sensing Resistor • On−Board 5 V Reference Voltage for Precise Thresholds/Hysteresis Adjustments • ±1 A peak Current Drive Capability • Power Good Output Management Signal • LLC Controller Operates from 25 kHz to 500 kHz • On Board 600 V High−Voltage Drivers • 1 A/0.5 A Sink/Source Capability • Minimum Frequency Precision Down to ±3% Over Temperature Range • A Version with Dual Ground Pinout (No Skip), B Version with Single Ground and Skip Operation for the LLC Controller • 20 V Operation • These are Pb−Free Devices • Internally Fixed Dead−Time Value of 300 ns • Adjustable Soft−Start Sequence • Fast Fault Input with Soft−Start Trigger for Immediate Auto−Recovery Protection Typical Applications • Multi Output ATX Power Supplies (A version) • Flat TVs Power Supplies (B version) © Semiconductor Components Industries, LLC, 2012 December, 2012 − Rev. 1 1 Publication Order Number: NCP1910/D Free Datasheet http://www.datasheet4u.com/ 1 page NCP1910 OVP2 FB Vfold VCTRL RpuFlBl down 107% Vpref VOVP2 + − 105% Vpref VOVP VUVP 8% Vpref + − + − PFC_OPL PFC_OK “1” OVP2, “0” = ok 20 us filter Latched adjustable OVP2 PlaFtcCh_eOd VP2 Grand Reset PFC_BO “1” OVP, “0” = ok PFC_OVP Auto−recovery internal OVP “1” = UVP, “0” ok PFC_UVP VDD IVLD Vctrl(max) PFCflag 1deslaeyc Vctrl + − GRerasnedt Vctrl(min) − 0.1 V PFC_BO If PFC issues an abnormal situation, then latch off PFC_abnormal R Q latched Q S PFC_BO Latch Grand Reset Dynamic Response Enhancer ““01”” o=kbelow 5% reg PFC_SKIP (va0oc.lt6tiavVagteecldias.m) p R Q PFC_OK Q S VLD 95% Vpref Vpref Vfold(max) Vctrl OTA Cloifs“e1d” “1” = FB > Vpref Grand Reset PFC_BO Ict(fold) Grand Reset PFC_BO “1” open “0” close PFC drive signal The “PFC_OK” toggles high when: − VLD is low − PFC issues a driving pulse The “PFC_OK” toggles low when: − Vctrl stays out of window [Vctrl,min to Vctrl,max] > 1 sec − at this point, the latch is reset and the “PFC_OK” output goes low. LBO VLBO VLBOT + − ILBO “1” BO NOTOK, “0” BOK PFC_BO Vctrl(min) BO delay SQ Q R A VLBO^2 B VDD Multiplier Latch Onoff UVLO TSD PFC_SKIP PFC_OL PFC_OVP PFC_BO PFC_OK SQ Q R CS ICS VM ICS ICS VLBO^2 Vpref Vdd Vctrl−Vctrl(min) ICS VLBO2 4(Vctrl * Vctrl(min)) ICS x VLBO^2 ICt(min) ICt ICS x VLBO > 275 uA + “1” = OPL − PFC_OPL ICS > 200 uA PFC_OL + − “1” = OCPPFC_OCP “V0p”r/e“f1/”10%Vpref Oscillator section Vcc DRV Figure 4. Internal PFC Block Diagram http://onsemi.com 5 Free Datasheet http://www.datasheet4u.com/ 5 Page NCP1910 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit LLC CONTROL SECTION DRIVE OUTPUT TLr Output voltage rise−time @ CL = 1 nF, 10−90% of output signal TLf Output voltage fall−time @ CL = 1 nF, 10−90% of output signal RLOH Source resistance RLOL Sink resistance DTL Dead time, measured between 50% of the rise and fall edge IHV,leak Leakage current on high voltage pins to GND (600 Vdc) PROTECTIONS 23, 20 − 40 − ns 23, 20 − 20 − ns 23, 20 − 12 26 W 23, 20 − 5 11 W 23, 20 268 327 386 ns 22, 23, 24 − − 5 mA IBOadj Input bias current, BOadj pin 5 − 15 − nA VBOadjH BO comparator hysteresis 5 − 100 − mV tBOK BO comparator Integrating Filter Time Constant from High to Low 5 − 150 − ms tBONOTOK BO comparator Integrating Filter Time Constant from Low to High 5 − 20 − ms VCS1 Current−sense pin level that resets the soft−start capacitor 15 0.95 1 1.05 V VCS2 Current−sense pin level that permanently latches off the circuit 15 1.42 1.5 1.58 V tCS Propagation delay from VCS1/2 activation to respective action 15 − − 500 ns 3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later, when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge slope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltage is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms. 4. Guaranteed by design. http://onsemi.com 11 Free Datasheet http://www.datasheet4u.com/ 11 Page

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