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PDF NLSX3014 Data sheet ( Hoja de datos )
| Número de pieza | NLSX3014 | |
| Descripción | Translator | |
| Fabricantes | ON Semiconductor | |
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NLSX3014
4-Bit 100 Mb/s Configurable
Dual-Supply Level
Translator
The NLSX3014 is a 4−bit configurable dual−supply bidirectional
level translator without a direction control pin. The I/O VCC− and I/O
VL−ports are designed to track two different power supply rails, VCC
and VL respectively. The VCC supply rail is configurable from 1.3 V
to 4.5 V while the VL supply rail is configurable from 0.9 V to (VCC
− 0.4) V. This allows lower voltage logic signals on the VL side to be
translated into higher voltage logic signals on the VCC side, and
vice−versa. Both I/O ports are auto−sensing; thus, no direction pin is
required.
The Output Enable (EN) input, when Low, disables both I/O ports
by putting them in 3−state. This significantly reduces the supply
currents from both VCC and VL. The EN signal is designed to track
VL.
Features
• Wide High−Side VCC Operating Range: 1.3 V to 4.5 V
Wide Low−Side VL Operating Range: 0.9 V to (VCC − 0.4) V
• High−Speed with 100 Mb/s Guaranteed Date Rate for VL > 1.6 V
• Low Bit−to−Bit Skew
• Overvoltage Tolerant Enable and I/O Pins
• Non−preferential Powerup Sequencing
• Small packaging: 1.7 mm x 2.0 mm UQFN12
• This is a Pb−Free Device
Typical Applications
• Mobile Phones, PDAs, Other Portable Devices
http://onsemi.com
MARKING
DIAGRAM
1
UQFN12
MU SUFFIX
CASE 523AE
UTMG
G
UT = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
LOGIC DIAGRAM
EN VL VCC GND
I/O VL1
I/O VCC1
I/O VL2
I/O VL3
I/O VCC2
I/O VCC3
© Semiconductor Components Industries, LLC, 2008
July, 2008 − Rev. 4
I/O VL4
I/O VCC4
PIN ASSIGNMENT
EN
VL 1 12 11 VCC
I/O VL1
I/O VL2
I/O VL3
2
3
4
10 I/O VCC1
9 I/O VCC2
8 I/O VCC3
I/O VL4 5 6 7 I/O VCC4
GND
(TOP VIEW)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
1 Publication Order Number:
NLSX3014/D
Free Datasheet http://www.datasheet4u.com/
1 page  
NLSX3014
TIMING CHARACTERISTICS
Symbol
tR−VCC
Parameter
I/O VCC Rise Time
(Output = I/O_VCC)
Test Conditions
(Note 8)
CIOVCC = 15 pF
VCC (V)
(Note 9)
1.3 to 4.5
> 2.0
VL (V)
(Note 10)
0.9 to (VCC – 0.4)
> 1.6
−405C to +855C
Typ
Min (Note 11) Max
1.3 1.7
0.9 1.1
Unit
ns
tF−VCC
I/O VCC Falltime
(Output = I/O_VCC)
CIOVCC = 15 pF
1.3 to 4.5
> 2.0
0.9 to (VCC – 0.4)
> 1.6
0.8 1.2 ns
0.6 1.0
tR−VL
I/O VL Risetime
(Output = I/O_VL)
CIOVL = 15 pF
1.3 to 4.5
> 2.0
0.9 to (VCC – 0.4)
> 1.6
2.7 3.0 ns
0.8 1.0
tF−VL
I/O VL Falltime
(Output = I/O_VL)
CIOVL = 15 pF
1.3 to 4.5
> 2.0
0.9 to (VCC – 0.4)
> 1.6
0.8 1.0 ns
0.7 0.8
ZO−VCC I/O VCC One−Shot
Output Impedance
1.3 to 4.5 0.9 to (VCC – 0.4)
30
W
ZO−VL
I/O VL One−Shot
Output Impedance
1.3 to 4.5 0.9 to (VCC – 0.4)
30
W
tPD_VL−VCC Propagation Delay
(Output = I/O_VCC,
tPHL, tPLH)
CIOVCC = 15 pF
1.3 to 4.5
> 2.0
0.9 to (VCC – 0.4)
> 1.6
15 17 ns
45
tPD_VCC−VL Propagation Delay
(Output = I/O_VL,
tPHL, tPLH)
CIOVL = 15 pF
1.3 to 4.5
> 2.0
0.9 to (VCC – 0.4)
> 1.6
10 11 ns
34
tSK VL−VCC Channel−to−Channel
Skew (Output =
I/O_VCC)
CIOVCC = 15 pF
1.3 to 4.5
> 2.0
0.9 to (VCC – 0.4)
> 1.6
0.6 1 nS
0.2 0.8
tSK_VCC−VL Channel−to−Channel
Skew
(Output = I/O_VL)
CIOVCC = 15 pF
1.3 to 4.5
> 2.0
0.9 to (VCC – 0.4)
> 1.6
0.4 0.6 nS
0.2 0.3
Maximum Data Rate
(Output = I/O_VCC,
CIOVCC = 15 pF)
(Output = I/O_VL,
CIOVL = 15 pF)
1.3 to 4.5 0.9 to (VCC – 0.4)
> 2.0
> 1.6
60
100
Mb/s
8. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified.
9. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions.
10. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However,
during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V.
11. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
http://onsemi.com
5
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