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PDF NLSX4373 Data sheet ( Hoja de datos )
| Número de pieza | NLSX4373 | |
| Descripción | Translator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NLSX4373
2-Bit 20 Mb/s Dual-Supply
Level Translator
The NLSX4373 is a 2−bit configurable dual−supply bidirectional
auto sensing translator that does not require a directional control pin.
The VCC I/O and VL I/O ports are designed to track two different
power supply rails, VCC and VL respectively. The VCC supply rail is
configurable from 1.5 V to 5.5 V while VL supply rail is configurable
to 1.5 V to 5.5 V. This allows voltage logic signals on the VL side to
be translated into lower, higher or equal value voltage logic signals
on the VCC side, and vice−versa.
The NLSX4373 translator has open−drain outputs with integrated
10 kW pullup resistors on the I/O lines. The integrated pullup
resistors are used to pullup the I/O lines to either VL or VCC. The
NLSX4373 is an excellent match for open−drain applications such as
the I2C communication bus.
Features
• VL can be Less than, Greater than or Equal to VCC
• Wide VCC Operating Range: 1.5 V to 5.5 V
Wide VL Operating Range: 1.5 V to 5.5 V
• High−Speed with 20 Mb/s Guaranteed Date Rate
• Low Bit−to−Bit Skew
• Enable Input and I/O Lines have Overvoltage Tolerant (OVT) to
5.5 V
• Nonpreferential Powerup Sequencing
• Integrated 10 kW Pullup Resistors
• Small packaging: UDFN8, SO−8, Micro8
• This is a Pb−Free Device
Typical Applications
• I2C, SMBus, PMBus
• Low Voltage ASIC Level Translation
• Mobile Phones, PDAs, Cameras
Important Information
• ESD Protection for All Pins
− Human Body Model (HBM) > 7000 V
http://onsemi.com
8
1
UDFN8
MU SUFFIX
CASE 517AJ
MARKING
DIAGRAMS
VFM
G
VF = Specific Device Code
M = Date Code
G = Pb−Free Package
8
1
SO−8
D SUFFIX
CASE 751
8
SX4373
ALYW G
G
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
1
A
Y
W
G
Micro8
DM SUFFIX
CASE 846A
8
4373
AYW G
G
1
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
NLSX4373MUTAG
NLSX4373DR2G
Package
Shipping†
UDFN8 3000/Tape & Reel
(Pb−Free)
SO−8 2500/Tape & Reel
(Pb−Free)
NLSX4373DMR2G Micro8 4000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 3
1
Publication Order Number:
NLSX4373/D
Free Datasheet http://www.datasheet4u.com/
1 page  
NLSX4373
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS
(I/O test circuit of Figures 2 and 3, CLOAD = 15 pF, driver output impedance v 50 W, RLOAD = 1 MW)
−405C to +855C
(Notes 3 and 4)
Symbol
Parameter
VL = 1.5 V, VCC = 5.5 V
tRVCC I/O VCC Risetime
tFVCC I/O VCC Falltime
tRVL I/O VL Risetime
tFVL I/O VL Falltime
tPDVL−VCC Propagation Delay (Driving I/O VL)
tPDVCC−VL Propagation Delay (Driving I/O VCC)
tPPSKEW Part−to−Part Skew
Maximum Data Rate
Test Conditions
Min Typ Max
15
20
30
10
20
20
5
20
VL = 1.8 V, VCC = 2.8 V
tRVCC I/O VCC Risetime
tFVCC I/O VCC Falltime
tRVL I/O VL Risetime
tFVL I/O VL Falltime
tPDVL−VCC Propagation Delay (Driving I/O VL)
tPDVCC−VL Propagation Delay (Driving I/O VCC)
tPPSKEW Part−to−Part Skew
Maximum Data Rate
15
15
25
10
15
15
5
20
VL = 2.5 V, VCC = 3.6 V
tRVCC I/O VCC Risetime
tFVCC I/O VCC Falltime
tRVL I/O VL Risetime
tFVL I/O VL Falltime
tPDVL−VCC Propagation Delay (Driving I/O VL)
tPDVCC−VL Propagation Delay (Driving I/O VCC)
tPPSKEW Part−to−Part Skew
Maximum Data Rate
15
10
15
10
15
15
5
20
VL = 2.8 V, VCC = 1.8 V
tRVCC I/O VCC Risetime
tFVCC I/O VCC Falltime
tRVL I/O VL Risetime
tFVL I/O VL Falltime
tPDVL−VCC Propagation Delay (Driving I/O VL)
tPDVCC−VL Propagation Delay (Driving I/O VCC)
tPPSKEW Part−to−Part Skew
Maximum Data Rate
25
10
20
15
15
15
5
20
3. Typical values are for VCC = +3.3 V, VL = +1.8 V and TA = +25°C.
4. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.
Unit
ns
ns
ns
ns
ns
ns
nS
Mb/s
ns
ns
ns
ns
ns
ns
nS
Mb/s
ns
ns
ns
ns
ns
ns
nS
Mb/s
ns
ns
ns
ns
ns
ns
nS
Mb/s
http://onsemi.com
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
NLSX4373
PACKAGE DIMENSIONS
−X−
A
SO−8
CASE 751−07
ISSUE AJ
B
−Y−
−Z−
H
85
S 0.25 (0.010) M Y M
1
4
K
G
D
C
SEATING
PLANE
N X 45_
0.10 (0.004)
M
J
0.25 (0.010) M Z Y S X S
SOLDERING FOOTPRINT*
1.52
0.060
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0_ 8_ 0_ 8_
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
ǒ ǓSCALE 6:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet NLSX4373.PDF ] | |
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