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PDF HIP1012A Data sheet ( Hoja de datos )
| Número de pieza | HIP1012A | |
| Descripción | Dual Power Distribution Controller | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
HIP1012, HIP1012A
November 1999 File Number 4419.4
Dual Power Distribution Controller
The HIP1012 is a HOT SWAP dual supply power distribution
controller. Two external N-Channel MOSFETs are driven to
distribute power while providing load fault isolation.
At turn-on, the gate of each external N-Channel MOSFET is
charged with a 10µA current source. Capacitors on each
gate (see the Typical Application Diagram), create a
programmable ramp (soft turn-on) to control inrush currents.
A built in charge pump supplies the gate drive for the 12V
supply N-Channel MOSFET switch.
Over current protection is facilitated by two external current
sense resistors. When the current through either resistor
exceeds the user programmed value the controller enters the
current regulation mode. The time-out capacitor, CTIM, starts
charging as the controller enters the time out period. Once
CTIM charges to a 2V threshold, the N-Channel MOSFETs
are latched off. In the event of a fault at least three times the
current limit level, the N-Channel MOSFET gates are pulled
low immediately before entering time out period. The
controller is reset by a rising edge on either PWRON pin.
Choosing the voltage selection mode the HIP1012 controls
either +12V/5V or +3.3V/+5V supplies.
For those applications where voltage tolerance is a concern
the HIP1012A has a minimum nominal over current threshold
voltage of 50mV as compared to 100mV for the HIP1012.
Ordering Information
PART NUMBER
HIP1012CB
HIP1012ACB
HIP1012CB-T
HIP1012ACB-T
TEMP.
RANGE (oC)
PACKAGE
-0 to 70 14 Ld SOIC
-0 to 70 14 Ld SOIC
Tape and Reel
PKG.
NO.
M14.15
M14.15
Features
• HOT SWAP Dual Power Distribution Control for +5V and
+12V or +5V and +3.3V
• Provides Fault Isolation
• Programmable Current Regulation Level
• Programmable Time Out
• Charge Pump Allows the Use of N-Channel MOSFETs
• Power Good and Over Current Latch Indicators
• Enhanced Over Current Sensitivity Available
• Redundant Power On Controls
• Adjustable Turn-On Ramp
• Protection During Turn-On
• Two Levels of Current Limit Detection Provide Fast
Response to Varying Fault Conditions
• Less Than 1µs Response Time to Dead Short
• 3µs Response Time to 200% Current Overshoot
Applications
• Redundant Array of Independent Disks (RAID) System
• Power Distribution Control
• Hot Plug™, Hot Swap Components
Pinout
HIP1012 (SOIC)
TOP VIEW
3/12VS 1
3/12VG 2
VDD
MODE/
PWRON1
PWRON2
5VG
3
4
5
6
5VS 7
14 3/12VISEN
13 RILIM
12 GND
11 CPUMP
10 CTIM
9 PGOOD
8 5VISEN
Typical Application Diagram
OPTIONAL
VDD RFILTER
CFILTER
CPUMP
RSENSE
12V
RGATE
HIP1012
CGATE
POWER ON
INPUTS
3/12VS3/12VISEN
3/12VG RILIM
VDD
GND
M/PON1 CPUMP
PWRON2 CTIM
5V
RGATE 5VG
PGOOD
5VS 5ISEN
CGATE
RSENSE
RLOAD
RILIM
CTIM
5V OR 3.3V
RLOAD
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Hot Plug™ is a trademark of Core International, Inc.
1 page  
HIP1012, HIP1012A
Electrical Specifications VDD = 12V, CVG = 0.01µF, CTIM = 0.1µF, RSENSE = 0.1Ω, CBULK = 220µF, ESR = 0.5Ω, TA = TJ = 0oC to 70oC,
Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Gate Turn-On Time
Gate Turn-On Current
3X Gate Discharge Current
5V Under Voltage Threshold
3.3V Under Voltage Threshold
3.3/5VG High Voltage
tON5V
ION5V
3XdisI
5VVUV
3.3VVUV
3/5VG
CVG = 0.01µF
CVG = 0.01µF
CVG = 0.01µF, PWRON = Low
-5-
8 10 12
0.5 0.75
-
4.35 4.5 4.65
2.65 2.8 2.95
11.2 11.9
-
ms
µA
A
V
V
V
SUPPLY CURRENT AND IO SPECIFICATIONS
VDD Supply Current
VDD POR Rising Threshold
VDD POR Falling Threshold
Current Limit Time-Out
PWRON Pull-up Voltage
IVDD
TILIM
CTIM = 0.1µF
PWRN_V PWRON pin open
4 8 10 mA
9.5 10.0 10.7
V
9.3 9.8 10.3 V
16 20 24 ms
1.8 2.4 3.2
V
PWRON Rising Threshold
PWR_Vth
1.1 1.5
2
V
PWRON Hysteresis
PWR_hys
0.1 0.2 0.3
V
PWRON Pull-Up Current
PWRN_I
60 80 100 µA
Current Limit Time-Out Threshold (CTIM)
CTIM Charging Current
CTIM Discharge Current
CTIM Pull-Up Current
RILIM Pin Current Source Output
Charge Pump Output Current
Charge Pump Output Voltage
CTIM_Vth
CTIM_I
CTIM_disI
CTIM_disI
RILIM_Io
Qpmp_Io
Qpmp_Vo
VCTIM = 8V
CPUMP = 0.1µF, CPUMP = 16V
No load
1.8 2 2.2
8 10 12
1.7 2.6 3.5
3.5 5 6.5
90 100 110
320 560 800
17.2 17.4
-
V
µA
mA
mA
µA
µA
V
Charge Pump Output Voltage - Loaded
Qpmp_VIo Load current = 100µA
16.2 16.7
-
V
Charge Pump POR Rising Threshold
Qpmp+Vth
15.6 16 16.5
V
Charge Pump POR Falling Threshold
Qpmp-Vth
15.2 15.7 16.2
V
HIP1012 Description and Operation
The HIP1012 is a multi featured dual power supply
distribution controller, including programmable current
limiting regulation and time to latch off. Additionally the
HIP1012 operates both as a +3.3V and 5V or a +5V and
+12V power supply controller with each mode having
appropriate Under Voltage (UV) fault notification levels.
Upon initial power up HIP1012 can either isolate the
voltage supply from the load by holding the external
N-Channel MOSFET switches off or apply the supply rail
voltage directly to the load for true hot swap capability. In
either case the HIP1012 turns on in a soft start mode
protecting the supply rail from sudden current loading. If
either PWRON pin is pulled low the HIP1012 will be in true
hot swap mode. Both PWRON pins must be high to turn off
the HIP1012 thus isolating the power supply from the load
through the external FETs.
At turn-on, the gate capacitor of each external N-Channel
MOSFET is charged with a 10µA current source. These
capacitors create a programmable ramp (soft turn-on). A
charge pump supplies the gate drive for the 12V supply
switch driving that gate to 17V.
The load currents pass through two external current sense
resistors. When the voltage across either resistor exceeds
the user programmed Over Current (OC) voltage threshold
value, (see Table 1) the controller enters current regulation.
At this time the time-out capacitor, CTIM, starts charging with
a 10µA current source and the controller enters the time out
period. The length of the time out period is set by the single
external capacitor (see Table 2) placed from the CTIM pin
(pin 10) to ground and is characterized by a lowered gate
drive voltage to the appropriate external N-Channel
MOSFET. Once CTIM charges to 2V, an internal comparator
is tripped resulting in both N-Channel MOSFETs being
latched off.
5
5 Page 
BUS
GENERIC
FIGURE 13. HIP1012EVAL1 EVAL BOARD
LOAD
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet HIP1012A.PDF ] | |
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