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HIP6500B PDF даташит

Спецификация HIP6500B изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «Multiple Linear Power Controller with ACPI Control Interface».

Детали детали

Номер произв HIP6500B
Описание Multiple Linear Power Controller with ACPI Control Interface
Производители Intersil Corporation
логотип Intersil Corporation логотип 

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HIP6500B Даташит, Описание, Даташиты
TM
Data Sheet
HIP6500B
May 2000
File Number 4870
Multiple Linear Power Controller with
ACPI Control Interface
The HIP6500B complements either an HIP6020 or an HIP6021
in ACPI-compliant designs for microprocessor and computer
applications. The IC integrates two linear controllers and two
regulators, switching, monitoring and control functions into a
20-pin SOIC package. One linear controller generates the
3.3VDUAL voltage plane from the ATX supply’s 5VSB output,
powering the PCI slots through an external pass transistor
during sleep states (S3, S4/S5). A second transistor is used to
switch in the ATX 3.3V output for operation during S0 and
S1/S2 (active) operating states. The second linear controller
supplies the computer system’s 2.5V/3.3V memory power
through an external pass transistor in active states. During S3
state, an integrated pass transistor supplies the 2.5V/3.3V
sleep power. A third controller powers up the 5VDUAL plane by
switching in the ATX 5V output in active states, and the ATX
5VSB in sleep states. The two internal regulators consist of a
low current 3.3V sleep output and a dedicated, noise-free 2.5V
clock chip supply. The HIP6500B’s operating mode (active
outputs or sleep outputs) is selectable through two digital
control pins, S3 and S5. Further control of the logic governing
activation of different power states is offered through two
configuration pins, EN3VDL and EN5VDL. In active state, the
3.3VDUAL linear regulator uses an external N-Channel pass
MOSFET to connect the output directly to the 3.3V input
supplied by an ATX (or equivalent) power supply, for minimal
losses. In sleep state, power delivery on the 3.3VDUAL output is
transferred to an NPN transistor, also external to the controller.
Active state power delivery for the 2.5/3.3VMEM output is
performed through an external NPN transistor, or an NMOS
switch for the 3.3V setting. In sleep state, conduction on this
output is transferred to an internal pass transistor. The 5VDUAL
output is powered through two external MOS transistors. In
sleep states, a PMOS (or PNP) transistor conducts the current
from the ATX 5VSB output; while in active state, current flow is
transferred to an NMOS transistor connected to the ATX 5V
output. Similar to the 3.3VDUAL output, the operation of the
5VDUAL output is dictated not only by the status of the S3 and
S5 pins, but that of the EN5VDL pin as well. The 3.3VSB
internal regulator is active for as long as the ATX 5VSB voltage
is applied to the chip, and derives its output current from the
5VSB pin. The 2.5VCLK output is only active during S0 and S1,
and uses the 3V3 pin as input source for its internal pass
element.
Ordering Information
PART NUMBER
HIP6500BCB
HIP6500BEVAL1
TEMP.
RANGE (oC)
PACKAGE
0 to 70 20 Ld SOIC
Evaluation Board
PKG.
NO.
M20.3
Features
• Provides 5 ACPI-Controlled Voltages
- 5V Active/Sleep (5VDUAL)
- 3.3V Active/Sleep (3.3VDUAL)
- 2.5V/3.3V Active/Sleep (2.5/3.3VMEM)
- 3.3V Always Present (3.3VSB)
- 2.5V Clock (Active Only) (2.5VCLK)
• Excellent Output Voltage Regulation
- 3.3VDUAL Output: ±2% Over Temperature; Sleep State
Only
- 2.5V/3.3VMEM Output: ±2% Over Temperature; Both
Operational States (3.3V setting in sleep only)
- 2.5VCLK and 3.3VSB Output: ±2% Over Temperature
• Small Size
- Very Low External Component Count
• Selectable Memory Output Voltage Via FAULT/MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
Applications
Motherboard Power Regulation for ACPI-Compliant
Computers
Pinout
HIP6500B
(SOIC)
TOP VIEW
VSEN2 1
5VSB 2
3V3SB 3
3V3DLSB 4
3V3DL 5
VCLK 6
3V3 7
EN5VDL 8
S3 9
S5 10
20 EN3VDL
19 DRV2
18 5V
17 12V
16 SS
15 5VDL
14 5VDLSB
13 DLA
12 FAULT/MSEL
11 GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000









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HIP6500B Даташит, Описание, Даташиты
Block Diagram
12V
3V3DLSB
3V3DL
5V 3V3
5VSB
5VDLSBDLA
EA4
12V MONITOR
TO 5VSB
10.8V/9.8V
3V3SB
EA3 +
-
TO
UV
DETECTOR
FAULT/MSEL
UV DETECTOR
5V MONITOR
4.5V/4.25V
5VSB POR
4.4V/3.2V
3V3 MONITOR
2.97V/2.8V
TEMPERATURE
MONITOR
(TMON)
MONITOR AND CONTROL
TO
UV DETECTOR
+ EA3
-
TO 3V3
+
1.265V
-
TO 5V
5VDL
40µA
TO 5VSB
10µA
+
3.75V
-
UV COMPARATOR
TO
UV DETECTOR
EA2
-
+
GND
SS
S3 S5 EN3VDL EN5VDL
FIGURE 1.
VCLK
DRV2
VSEN2









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HIP6500B Даташит, Описание, Даташиты
Simplified Power System Diagram
+5VIN
+12VIN
+5VSB
+3.3VIN
Q2
3.3VDUAL
3.3V
FAULT/MSEL
Q3
3.3VSB
3.3V
SHUTDOWN
SX
ENXVDL
2
2
Typical Application
+5VIN
+12VIN
+5VSB
+3.3VIN
HIP6500B
LINEAR
REGULATOR
LINEAR
CONTROLLER
LINEAR
CONTROLLER
LINEAR
REGULATOR
HIP6500B
CONTROL
LOGIC
FIGURE 2.
Q1
VMEM
2.5V/3.3V
VCLK
2.5V
Q4
Q5
5VDUAL
5V
VOUT1
3.3VSB
COUT1
Q2
VOUT3
3.3VDUAL
Q3
COUT3
FAULT
SLP_S3
SLP_S5
EN5VDL
EN3VDL
SHUTDOWN
12V
3V3SB
3V3
5V
3V3DLSB
5VSB
DRV2
Q1
VSEN2
3V3DL
FAULT/MSEL
RSEL
S3
S5
EN5VDL
EN3VDL
SS
CSS
HIP6500B
GND
COUT2
VCLK
COUT4
5VDLSB
DLA
5VDL
Q5
COUT5
VOUT2
2.5/3.3VMEM
VOUT4
2.5VCLK
Q4
VOUT5
5VDUAL
FIGURE 3.
3










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