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HIP7010B PDF даташит

Спецификация HIP7010B изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «J1850 Byte Level Interface Circuit».

Детали детали

Номер произв HIP7010B
Описание J1850 Byte Level Interface Circuit
Производители Intersil Corporation
логотип Intersil Corporation логотип 

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HIP7010B Даташит, Описание, Даташиты
HIP7010
ADVANCE INFORMATION
August 1996
J1850 Byte Level Interface Circuit
Features
• Fully Supports VPW (Variable Pulse Width) Messaging
Practices of SAE J1850 Standard for Class B Data
Communications Network Interface
- 3-Wire, High-Speed, Synchronous, Serial Interface
• Reduces Wiring Overhead
• Directly Interfaces with 68HC05 and 68HC11 Style SPI
Ports
• 1MHz, 8-Bit Transfers Between Host and HIP7010
Minimize Host Service Requirements
• Automatically Transmits Properly Framed Messages
• Prepends SOF to First Byte and Appends CRC to Last
Byte
• Fail-Safe Design Including, Slow Clock Detection
Circuitry, Prevents J1850 Bus Lockup Due to System
Errors or Loss of Input Clock
• Automatic Collision Detection
• End of Data (EOD), Break, Idle Bus, and Invalid Symbol
(Noise/Illegal Symbols) Detection
• Supports In-Frame Responses with Generation of
Normalization Bits (NB) for Type 1, Type 2, and Type 3
Messages
• Wait-For-Idle Mode Reduces Host Overhead During
Non-Applicable Messages
• Status Register Flags Provide Information on Current
Status of J1850 Bus
• Serial I/O Pins are Active Only During Transfers - Bus
Available for Other Devices 95% of the Time
• TEST Pin Provides Built-in-Test Capabilities for
In-System Diagnostics and Factory Testing
• High Speed (4X) Receive Mode for Production and
Diagnostic Testing/Programming
• Operates with Wide Range of Input Clock Frequencies
• Power-Saving Power-Down Mode
• Full -40oC to +125oC Operating Range
• Single 3.0V to 6.0V Supply
Description
The Intersil HIP7010, J1850 Byte Level Interface Circuit, is a
member of the Intersil family of low-cost multiplexed wiring
ICs. The integrated functions of the HIP7010 provide the
system designer with components key to building a “Class B”
multiplexed communications network interface, which fully
conforms to the VPW Multiplexed Wiring protocol specified
in the SAE J1850 Standard. The HIP7010 is designed to
interface with a wide variety of Host microcontrollers via a
standard three wire, high-speed (1MHz), synchronous, serial
interface. The HIP7010 automatically produces properly
framed VPW messages, prepending the Start of Frame
(SOF) symbol and calculating and appending the CRC
check byte. All circuitry needed to decode incoming mes-
sages, to validate CRC bytes, and to detect Breaks, End of
Data (EOD), Idle bus, and illegal symbols is included. In-
Frame Responses (IFRs) are fully supported for Type 1,
Type 2, and Type 3 messages, with the appropriate Normal-
ization Bit automatically generated. The HCMOS design
allows proper opeSration at various input frequencies from
2MHz to 12MHz. Connection to the J1850 Bus is via a Inter-
sil HIP7020.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
PKG. NO.
HIP7010P
-40 +125 14 Lead Plastic DIP
E14.3
HIP7010B
-40 +125 14 Lead Plastic SOIC (N) M14.15
Pinout
HIP7010 (SOIC, PDIP)
TOP VIEW
IDLE 1
VPWIN 2
VPWOUT 3
VDD 4
RESET 5
TEST 6
SACTIVE 7
14 RDY
13 STAT
12 CLK
11 VSS
10 SIN
9 SOUT
8 SCK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 3644.2









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HIP7010B Даташит, Описание, Даташиты
HIP7010
Block Diagram
10
SIN
A
BMUX
C
LSB
MSB
OUTPUT DATA
DATA SHIFT REGISTER
DECODED VPW IN
J1850 VPW SYMBOL
ENCODER/DECODER
3
VPWOUT
2
VPWIN
9
SOUT
A
MUX
B
STATUS/CONTROL BYTE
CRC GENERATOR/CHECKER
SCK
IDLE
RDY
STAT
CLK
RESET
TEST
SACTIVE
8
1
14
13
12
5
6
7
TIMING
GENERATOR
Pin Description
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIN NAME
IDLE
VPWIN
VPWOUT
VDD
RESET
TEST
SACTIVE
SCK
SOUT
SIN
VSS
CLK
STAT
RDY
IN/OUT
OUT
IN
OUT
-
IN
IN
OUT
OUT
OUT
IN
-
IN
IN
IN
STATE MACHINE
AND CONTROL LOGIC
VDD 4
VSS 11
PIN DESCRIPTION
CMOS Output
CMOS Schmitt (No VDD Diode)
CMOS Output
Power Supply
CMOS Schmitt (No VDD Diode)
CMOS Input with Pull-Down
CMOS Output
Three-State with Pull-Down
Three-State with Pull-Down
CMOS Input with Pull-Down
Ground
CMOS Schmitt (No VDD Diode)
CMOS Input with Pull-Down
CMOS Input with Pull-Down
2









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HIP7010B Даташит, Описание, Даташиты
HIP7010
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7.0V
Input or Output Voltage
Pins with VDD Diode . . . . . . . . . . . . . . . . . . . .-0.3V to VDD +0.3V
Pins without VDD Diode . . . . . . . . . . . . . . . . . . . . -0.3V to +10.0V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2500 Gates
Thermal Resistance
θJA
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . .+100oC/W
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+120oC/W
Maximum Package Power Dissipation at +125oC
DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250mW
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mW
Operating Temperature Range (TA) .
Storage Temperature Range (TSTG).
Junction Temperature . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
- 40oC
- 65oC
......
to
to
..
+125oC
+150oC
+150oC
Lead Temperature (Soldering, 10s). . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +3.0V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . -40oC to +125oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .(0.8VDD) to VDD
Input Rise and Fall Time
CMOS Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ns Max
CMOS Schmitt Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .Unlimited
Electrical Specifications TA = -40oC to +125oC, VDD = 5VDC ±10%, Unless Otherwise Specified
PARAMETERS
SYMBOL CONDITIONS
MIN TYP
Supply Current
Operating Current
Power-Down Mode (Note 1)
Clock Stopped (Note 2)
Input High Voltage
IOP
IPD
ISTOP
CLK = 2.0 MHz
PD = 1
CLK = VSS or VDD
-
-
-
1.0
50
5.0
CMOS Level (SIN, STAT, RDY, TEST)
Schmitt Trigger (RESET, CLK, VPWIN)
Input Low Voltage
VIH
0.7VDD
0.8VDD
-
-
CMOS Level (SIN, STAT, RDY, TEST)
Schmitt Trigger (RESET, CLK, VPWIN)
High Level Input Current
VIL
VSS
VSS
-
-
(CLK, VPWIN, RESET)
IIH VIN = VDD
Input Buffer with Pull-Down (SIN, TEST, STAT, RDY)
-1 0.001
100 200
Low Level Input Current
(CLK, VPWIN, RESET)
IIL VIN = VSS
Input Buffer with Pull-Down (SIN, TEST, STAT, RDY)
-1 -0.001
-10 -0.01
Output High Voltage
(SCK, SOUT, VPWOUT, IDLE, SACTIVE)
Output Low Voltage
VOH
ILOAD = 0.8 mA
VDD-0.8
-
(SCK, SOUT, VPWOUT, IDLE, SACTIVE)
High Impedance Leakage Current
VOL ILOAD = -1.6 mA
-
-
Three-State with Pull-Down (SCK, SOUT)
Schmitt Trigger Hysteresis Voltage
(RESET, CLK, VPWIN)
IOZ
VHYS
VOUT = VDD
VOUT = VSS
100 200
-10
0.2 0.5
NOTES:
1. SIN, STAT, RDY, and TEST = VSS; SACTIVE, SCK, and SOUT unconnected; VPWIN = VDD; CLK = 10MHz.
2. SIN, STAT, RDY, and TEST = VSS; SACTIVE, SCK, and SOUT unconnected; VPWIN = VDD; PD = 1.
MAX
5.0
150
50
VDD
VDD
0.3VDD
0.2VDD
1
500
1
10
-
0.4
500
10
2.0
UNITS
mA
µA
µA
V
V
V
V
µA
µA
µA
µA
V
V
µA
µA
V
3










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